F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 61/154:

LINE COMPARE REGISTER

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®
Display memory addresses are affected by CR17 bit
6 as shown in the table below:
Logical
Physical Memory Address
Memory
Byte
Word
Address
Mode
Mode
MA00
A00
Note 1
MA01
A01
A00
MA02
A02
A01
MA03
A03
A02
MA04
A04
A03
MA05
A05
A04
MA06
A06
A05
MA07
A07
A06
MA08
A08
A07
MA09
A09
A08
MA10
A10
A09
MA11
A11
A10
MA12
A12
A11
MA13
A13
A12
MA14
A14
A13
MA15
A15
A14
Note 1 = A13 * NOT CR17 bit 5
+ A15 * CR17 bit 5
Note 2 = A12 xor (A14 * XR04 bit 2)
Note 3 = A13 xor (A15 * XR04 bit 2)
Revision 0.7
LINE COMPARE
REGISTER (CR18)
Read/Write at I/O Address 3B5h/3D5h
Index 18h
Double Word
Group 3 Protection
Mode
Note 2
D7 D6 D5 D4 D3 D2 D1 D0
Note 3
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
7-0
A11
A12
A13
57
CRT Controller Registers
Line Compare Target
(Lower 8 bits)
Line Compare Target
These are the low order 8 bits of a 10-bit
register. The 9th and 10th bits are located in
the CRT Controller Overflow and Maxi-
mum Scan Line Registers, respectively.
This register is used to implement a split
screen function. When the scan line counter
value is equal to the contents of this register,
the memory address counter is cleared to 0.
The display memory address counter then
sequentially addresses the display memory
starting at address 0. Each subsequent row
address is generated by the addition of the
Offset Register contents. This register is not
affected by the double scanning bit (CR09
bit 7).
Preliminary 65510