F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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Page 62/154:

MEMORY DATA LATCH REGISTER

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MEMORY DATA LATCH
REGISTER (CR22)
Read only at I/O Address 3B5h/3D5h
Index 22h
D7 D6 D5 D4 D3 D2 D1 D0
Data Latch n Bit 7
Data Latch n Bit 6
Data Latch n Bit 5
Data Latch n Bit 4
Data Latch n Bit 3
Data Latch n Bit 2
Data Latch n Bit 1
Data Latch n Bit 0
This register may be used to read the state of
Graphics Controller Memory Data Latch 'n', where
'n' is controlled by the Graphics Controller Read
Map Select Register (GR04 bits 0–1) and is in the
range 0–3.
Writes to this register are not decoded and will be
ignored.
This is a standard VGA register which was not
documented by IBM.
ATTRIBUTE CONTROLLER TOGGLE
REGISTER (CR24)
Read only at I/O Address 3B5h/3D5h
Index 24h
D7 D6 D5 D4 D3 D2 D1 D0
Index (0) / Data (1)
Reserved
Palette Address Source
Attribute
Controller
Index
This register may be used to read back the state of
the attribute controller index/data latch.
Writes to this register are not decoded and will be
ignored.
This is a standard VGA register which was not
documented by IBM.
Revision 0.7
CRT Controller Registers
CLEAR VERTICAL
DISPLAY ENABLE FFh (CR3X)
Write only at I/O Address 3B5h/3D5h
Index 3xh
D7 D6 D5 D4 D3 D2 D1 D0
Writing odd data values to CRTC index 30-3Fh
causes the vertical display enable flip-flop to be
cleared.
The flip-flop is automatically set by
reaching vertical total. The effect of this is to force a
longer vertical retrace period. There are two side
effects of terminating vertical display enable early:
first, the screen blanks early for one frame causing a
minor visual disturbance and second, the sequencer
gives more display memory cycles to the CPU
because vertical display is not enabled.
Reads from this register are not decoded and will
return indeterminate data.
This is a standard VGA register which was not
documented by IBM.
58
Clear Vert Disp Ena FF
Ignored
Preliminary 65510