F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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DATA ROTATE REGISTER

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DATA ROTATE REGISTER (GR03)
Read/Write at I/O Address 3CFh
Index 03h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Rotate Count 0
Rotate Count 1
Rotate Count 2
Function Select
Reserved
2-0
Data Rotate Count
These bits specify the number of bits to
rotate to the right the data being written by
the CPU.
The CPU data bits are first
rotated, then subjected to the logical
operation as specified in the Function Select
bit field. The rotate function is active only if
the Graphics Mode register is programmed
for Write Mode 0.
4-3
Function Select
These Function Select bits specify the logical
function performed on the contents of the
processor latches (loaded on a previous
CPU read cycle) before the data is written to
display memory.
These bits operate as
follows:
Bit 4 Bit 3 Result
0
0
No change to the Data,
Latches are updated
0
1
Logical 'AND' between Data
and latched data
1
0
Logical 'OR' between Data
and latched data
1
1
Logical 'XOR' between Data
and latched data
7-5
Reserved (0)
Revision 0.7
Graphics Controller Registers
READ MAP SELECT REGISTER (GR04)
Read/Write at I/O Address 3CFh
Index 04h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
1-0
Read Map Select
This register is also used to 'reduce' 32 bits
of memory data to 8 bits for the CPU in the
4-plane graphics mode. These bits select the
memory plane from which the CPU reads
data in Read Mode 0. In Odd/Even mode,
bit-0 is ignored. In Quad mode, bits 0 and 1
are both ignored.
The four memory maps are selected as
follows:
Bit 1 Bit 0
0
0
0
1
1
0
1
1
7-2
Reserved (0)
61
Read Map Select 0
Read Map Select 1
Reserved
Map Selected
Plane 0
Plane 1
Plane 2
Plane 3
Preliminary 65510