F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 66/154:

GRAPHICS MODE REGISTER

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GRAPHICS MODE REGISTER (GR05)
Read/Write at I/O Address 3CFh
Index 05h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Write Mode
Reserved
Read Mode
Odd/Even Mode
Shift Register Mode
Reserved
1-0
Write Mode
For 16-bit writes, the operation is repeated
on the lower and upper bytes of CPU data.
1
0
Write Mode
0
0
Write mode 0 . Each of the four
display memory planes is written
with the CPU data rotated by the
number of counts in the Rotate
Register,
except
Set/Reset Register is enabled for
any of the four planes. When the
Set/Reset Register is enabled, the
corresponding plane is written
with the data stored in the
Set/Reset Register.
0
1
Write mode 1 . Each of the four
display memory planes is written
with the data previously loaded in
the processor latches.
latches are loaded during all read
operations.
1
0
Write mode 2. The CPU data bus
data is treated as the color value for
the addressed byte in planes 0-3.
All eight pixels in the addressed
byte are modified unless protected
by the Bit Mask register setting. A
logical 1 in the Bit Mask register
sets the corresponding pixel in the
addressed byte to the color
specified on the data bus. A 0 in
the Bit Mask register sets the
corresponding
addressed
Revision 0.7
when
the
2
3
These
(Continued on following page)
pixel
in
the
byte
to
the
62
Graphics Controller Registers
corresponding
pixel
processor latches. The Set/Reset
and Enable Set/Reset registers are
ignored. The Function Select bits
in the Data Rotate register are
used.
1
1
Write mode 3 . The CPU data is
rotated then logically ANDed with
the contents of the Bit Mask
register (GR08) and then treated as
the addressed data's bit mask,
while the contents of the Set/Reset
register is treated as the color
value.
A '0' on the data bus (mask)
causes the corresponding pixel in
the addressed byte to be set to the
corresponding
pixel
processor latches.
A '1' on the data bus (mask)
causes the corresponding pixel in
the addressed byte to be set to the
color value specified in the
Set/Reset register.
The Enable Set/Reset register is
ignored. The Data Rotate is used.
This write mode can be used to fill
an area with a single color and
pattern.
Reserved (0)
Read Mode
0 The CPU reads data from one of the
planes as selected in the Read Map
Select register.
1 The CPU reads the 8-bit result of the
logical comparison between all eight
pixels in the four display planes and
the contents of the Color Compare and
Color Don't Care registers. The CPU
reads a logical 1 if a match occurs for
each pixel and logical 0 if a mis-match
occurs.
In 16-bit read cycles, this
operation is repeated on the lower and
upper bytes.
Preliminary 65510
in
the
in
the