F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
Page 67/154:

Odd/Even Mode

Download datasheet (2Mb)Embed
PrevNext
®
4

Odd/Even Mode

0 All CPU addresses sequentially access all planes
1 Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This
option is useful for compatibility with the IBM CGA memory organization.
6-5
Shift Register Mode
These two bits select the data shift pattern used when passing data from the four memory planes through
the four video shift registers. If data bits 0-7 in memory planes 0-3 are represented as M0D0-M0D7,
M1D0-M1D7, M2D0-M2D7, and M3D0-M3D7 respectively, then the data in the serial shift registers is
shifted out as follows:
Last Bit
Shifted
65
Out
00:
M0D0 M0D1 M0D2 M0D3
M1D0 M1D1 M1D2 M1D3
M2D0 M2D1 M2D2 M2D3
M3D0 M3D1 M3D2 M3D3
01:
M1D0 M1D2 M1D4 M1D6
M1D1 M1D3 M1D5 M1D7
M3D0 M3D2 M3D4 M3D6
M3D1 M3D3 M3D5 M3D7
1x:
M3D0 M3D4 M2D0 M2D4
M3D1 M3D5 M2D1 M2D5
M3D2 M2D6 M3D2 M2D6
M3D3 M3D7 M2D3 M2D7
Note:
If the Shift Register is not loaded every character clock (see SR01 bits 2&4) then the four 8-bit
shift registers are effectively 'chained' with the output of shift register 1 becoming the input to
shift register 0 and so on. This allows one to have a large monochrome (or 4 color) bit map and
display one portion thereof.
Note:
If XR28 bit-4 is set (8-bit video path), GR05 bit-6 must be set to 0:
0x and XR28 bit-4=1:
7
Reserved (0)
Revision 0.7
Shift
Direction
M0D4 M0D5 M0D6 M0D7
M1D4 M1D5 M1D6 M1D7
M2D4 M2D5 M2D6 M2D7
M3D4 M3D5 M3D6 M3D7
M0D0 M0D2 M0D4 M0D6
M0D1 M0D3 M0D5 M0D7
M2D0 M2D2 M2D4 M2D6
M2D1 M2D3 M2D5 M2D7
M1D0 M1D4 M0D0 M0D4
M1D1 M1D5 M0D1 M0D5
M1D2 M1D6 M0D2 M0D6
M1D3 M1D7 M0D3 M0D7
M3D0 M2D0 M1D0 M0D0
M3D1 M2D1 M1D1 M0D1
M3D2 M2D2 M1D2 M0D2
M3D3 M2D3 M1D3 M0D3
M3D4 M2D4 M1D4 M0D4
M3D5 M2D5 M1D5 M0D5
M3D6 M2D6 M1D6 M0D6
M3D7 M2D7 M1D7 M0D7
63
Graphics Controller Registers
1st Bit
Out-
Shifted
put
Out
to:
Bit 0
Bit 1
Bit 2
Bit 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Preliminary 65510