F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 75/154:

COLOR PALETTE STATE REGISTER (DACSTATE)

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COLOR PALETTE
PIXEL MASK REGISTER (DACMASK)
Read/Write at I/O Address 3C6h
Group 6 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Pixel Mask Bit-0
Pixel Mask Bit-1
Pixel Mask Bit-2
Pixel Mask Bit-3
Pixel Mask Bit-4
Pixel Mask Bit-5
Pixel Mask Bit-6
Pixel Mask Bit-7
The contents of this register are logically ANDed
with the 8 bits of video data coming into the color
palette. Zero bits in this register therefore cause the
corresponding address input to the color palette to be
zero. For example, if this register is programmed
with 7, only color palette registers 0-7 would be
accessible; video output bits 3-7 would be ignored
and all color values would map into the lower 8
locations in the color palette.
This register is physically located on-chip (the chip
will respond directly if the internal color palette is
enabled).
This register is also implemented in
external color palette chips (RAMDACs) and the
external copy will be used if an external RAMDAC
is used instead (the on-chip mask register will be
ignored if the internal color palette is disabled).
Reads from this I/O location cause the PALRD/ pin
to be asserted if the internal color palette is disabled.
Writes to this I/O location cause the PALWR/ pin to
be asserted if the internal color palette is disabled. If
the internal color palette is disabled, the functionality
of this port is therefore determined by the external
palette chip.
Revision 0.7
Attribute Controller and Color Palette Registers
COLOR PALETTE
STATE REGISTER (DACSTATE)
Read only at I/O Address 3C7h
D7 D6 D5 D4 D3 D2 D1 D0
1-0
Palette State 1-0
Status bits indicate the I/O address of the last
CPU write to the Color Palette:
00
The last write was to 3C8h
(write mode)
11
The last write was to 3C7h
(read mode)
7-2
Reserved (0)
To allow saving and restoring the state of the video
subsystem, this register is required since the color
palette index register is automatically incremented
differently depending on whether the index is written
at 3C7h or 3C8h.
This register is physically located on-chip (PALRD/
is not asserted for reads from this I/O address
independent of whether the internal palette is enabled
or disabled).
71
Palette State 0
Palette State 1
Reserved
Preliminary 65510