F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 76/154:

COLOR PALETTE INDEX REGISTER (DACX)

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COLOR PALETTE
READ-MODE INDEX REGISTER (DACRX)
Write only at I/O Address 3C7h
Group 6 Protection
COLOR PALETTE
INDEX REGISTER (DACX)
Read/Write at I/O Address 3C8h
Group 6 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Color Palette Index 0
Color Palette Index 1
Color Palette Index 2
Color Palette Index 3
Color Palette Index 4
Color Palette Index 5
Color Palette Index 6
Color Palette Index 7
COLOR PALETTE
DATA REGISTERS (DACDATA 00-FF)
Read/Write at I/O Address 3C9h
Index 00h-FFh
Group 6 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Red 0
Red 1
Red 2
Red 3
Red 4
Red 5
(Red 6) (Green 6) (Blue 6)
(Red 7) (Green 7) (Blue 7)
The
color palette index and data registers are
physically located on-chip and in the external color
palette chip if one is used . Which set of registers is
used depends on whether the on-chip color palette is
enabled. If the on-chip palette is enabled, PALRD/
and PALWR/ are never active. If the on-chip color
palette is disabled, PALRD/ and PALWR/ are active
on I/O reads and writes respectively to enable the
external palette chip.
Revision 0.7
Attribute Controller and Color Palette Registers
In either case, the index register is used to point to
one of 256 data registers. Each data register is either
18 or 24 bits in length depending on the type of
palette chip used (6 or 8 bits each for red, green, and
blue), so the data values must be read as a sequence
of 3 bytes. After writing the index register (3C7h or
3C8h), data values may be read from or written to
the color palette data register port (3C9h) in
sequence: first red, then green, then blue, then repeat
for the next location if desired (the index is incre-
mented automatically by the palette logic).
The index may be written at 3C7h and may be read
or written at 3C8h. When the index value is written
to either port, it is written to both the index register
and a 'save' register. The save register (not the index
register) is used by the palette logic to point at the
current data register.
written to 3C7h (read mode), it is written to both the
index register and the save register, then the index
register is automatically incremented.
index value is written to 3C8h (write mode ), the
automatic incrementing of the index register does not
occur.
After the third of the three sequential data reads from
(or writes to) 3C9h is completed, the save and index
registers are both automatically incremented by the
palette logic. This allows the entire palette (or any
subset) to be read (written) by writing the index of
the first color in the set, then sequentially reading
(writing) the values for each color, without having to
reload the index every three bytes.
Access
The state of the RGB sequence is not saved; the user
1st
2nd
3rd
must access each three bytes in an uninterruptable
sequence (or be assured that interrupt service
Green 0
Blue 0
routines will not access the palette index or data
Green 1
Blue 1
registers). When the index register is written (at
Green 2
Blue 2
either port), the RGB sequence is restarted. Data
Green 3
Blue 3
value reads and writes may be intermixed; either
Green 4
Blue 4
reads or writes increment the palette logic's RGB
Green 5
Blue 5
sequence counter.
The palette's save register always contains a value
one less than the readable index value if the last
index write was to the 'read mode' port. The state is
saved for which port (3C7h or 3C8h) was last
written and that information is returned on reads
from 3C7h (PALRD/ is only asserted on reads from
3C8h and not on reads from 3C7h if the internal
palette is disabled). Writes to 3C7h or 3C8h cause
the PALWR/ pin to be asserted if the on-chip palette
is disabled.
If the on-chip color palette is disabled, the
functionality of the index and data ports is
determined by the external palette chip.
72
When the index value is
When the
Preliminary 65510