F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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Page 77/154:

Extension Registers

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Register
Register
Mnemonic
Group
Extension Register Name
XRX
--
Extension Index
XR00
Misc
Chip Version
XR01
Misc
Configuration
XR02
Misc
CPU Interface
XR04
Misc
Memory Control
XR06
Misc
Palette Control
XR0D
Misc
Auxiliary Offset
XR0E
Misc
Text Mode Control
XR0F
Misc
Software Flags 2
XR28
Misc
Video Interface
XR2B
Misc
Default Video
XR44
Misc
Software Flags
XR70
Misc
Setup / Disable Control
XR7F
Misc
Diagnostic
XR0B
Mapping
CPU Paging
XR0C
Mapping
Start Address Top
XR10
Mapping
Single/Low Map
XR11
Mapping
High Map
XR14
Compatibility
Emulation Mode
XR15
Compatibility
Write Protect
XR1F
Compatibility
Virtual EGA Switch
XR7E
Compatibility
CGA/Hercules Color Select
XR18
Alternate
FP Horizontal Display End
XR19
Alternate
FP H Sync Start / Half Line Compare
XR1A
Alternate
FP Horizontal Sync End
XR1B
Alternate
FP Horizontal Total
XR1C
Alternate
FP H Blank Start / H Panel Size
XR1D
Alternate
FP Horizontal Blank End
XR1E
Alternate
FP Offset
XR24
Flat Panel
FP Maximum Scan Line
XR2C
Flat Panel
Vertical Sync (FLM) Delay
XR2D
Flat Panel
Horizontal Sync (LP) Delay
XR2F
Flat Panel
Horizontal Sync (LP) Width
XR50
Flat Panel
Panel Format
XR51
Flat Panel
Display Type
XR52
Flat Panel
Power Down Control
XR53
Flat Panel
Line Graphics Override
XR54
Flat Panel
Panel Interface
XR55
Flat Panel
Horizontal Compensation
XR56
Flat Panel
Horizontal Centering
XR57
Flat Panel
Vertical Compensation
XR58
Flat Panel
Vertical Centering
XR59
Flat Panel
Vertical Line Insertion
XR5A
Flat Panel
Vertical Line Replication
XR5B
Flat Panel
Panel Power Sequencing Delay
XR5E
Flat Panel
ACDCLK Control
XR60
Flat Panel
Blink Rate Control
XR61
Flat Panel
SmartMap™ Control
XR62
Flat Panel
SmartMap™ Shift Parameter
XR63
Flat Panel
SmartMap™ Color Mapping Control
XR64
Flat Panel
FP Vertical Total
XR65
Flat Panel
FP Overflow
XR66
Flat Panel
FP Vertical Sync Start
XR67
Flat Panel
FP Vertical Sync End
XR68
Flat Panel
Vertical Panel Size
XR6C
Flat Panel
Programmable Output Drive
XR6E
Flat Panel
Polynomial FRC Control
XR7D
Flat Panel
Compensation Diagnostic
Reset Codes:
x = Not changed by RESET (indeterminate on power-up)
d = Set from the corresponding data bus pin on falling edge of RESET
h = Read-only Hercules Configuration Register Readback bits
Revision 0.7

Extension Registers

Index
--
00h
01h
02h
04h
06h
0Dh
0Eh
0Fh
28h
2Bh
44h
70h
7Fh
0Bh
0Ch
10h
11h
14h
15h
1Fh
7Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
24h
2Ch
2Dh
2Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Eh
60h
61h
62h
63h
64h
65h
66h
67h
68h
6Ch
6Eh
7Dh
73

Extension Registers

I/O
State After
Access
Address
Reset
RW
3D6h
- x x x x x x x
RO
3D7h
1 0 0 1 r r r r
RO
3D7h
d d d d d d d d
RW
3D7h
0 - 0 0 0 - 0 -
RW
3D7h
- - 0 0 - 0 - -
RW
3D7h
0 0 0 - - - - -
RW
3D7h
- - - - - - 0 0
RW
3D7h
- - - - 0 0 - -
R/W
3D7h
x x x x x x x x
RW
3D7h
- 0 - 0 - 0 - -
RW
3D7h
0 0 0 0 0 0 0 0
RW
3D7h
x x x x x x x x
RW
3D7h
0 - - - - - - -
RW
3D7h
0 0 x x x x 0 0
RW
3D7h
- - - 0 - 0 0 0
RW
3D7h
- - - - - - - 0
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
0 0 0 0 h h 0 0
RW
3D7h
0 0 0 0 0 0 0 0
RW
3D7h
0 - - - x x x x
RW
3D7h
- - x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- - - x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- x x - - - - -
RW
3D7h
x x x x x x x x
RW
3D7h
- - - x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x - x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x - 0 x x
RW
3D7h
0 - 0 - 0 0 0 0
RW
3D7h
- 0 - - x x - -
RW
3D7h
x x - x x x x x
RW
3D7h
- x x - - x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- x x - x x x x
RW
3D7h
- - - - x x x x
RW
3D7h
0 1 1 1 0 0 0 1
RW
3D7h
x x x x x x x x
RW
3D7h
1 0 0 0 0 0 1 1
RW
3D7h
x x x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x - x x x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
x x x - - x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- - - - x x x x
RW
3D7h
x x x x x x x x
RW
3D7h
- - - 0 0 0 - 0
RW
3D7h
1 0 1 1 1 1 0 1
RO
3D7h
- - - - - - - -
– = Not implemented (always reads 0)
r = Chip revision # (starting from 0000)
0/1 = Reset to 0 or 1 by falling edge of RESET
Preliminary 65510
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