F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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Page 79/154:

CONFIGURATION REGISTER

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CONFIGURATION REGISTER (XR01)
Read only at I/O Address 3B7h/3D7h
Index 01h
D7 D6 D5 D4 D3 D2 D1 D0
LB/: Bus Type
MC/: Bus Type
Reserved
XCV/: Transceiver Control
CD/: Clock Doubler
CFG5: Configuration Bit-5
CFG6: Configuration Bit-6
CFG7: Configuration Bit-7
These bits latch the state of memory address bus
(MA bus) bits 0-7 on the falling edge of RESET.
The state of bits 0-4 after RESET effect chip internal
logic as indicated below; bits 5-7 have no hardware
effect on the chip. MA0-7 have on-chip high-value
pullups which are enabled only at RESET.
This register is not related to the Virtual EGA
Switch register (XR1F).
1-0
CPU Bus Type
00 PI bus
01 MC bus
10 Local Bus
11 ISA bus
2
Reserved
3
Transceiver Control
0
External Transceivers
(Pin 50 on F65510 is VGARD Output)
(Pin 48 on T65510 is VGARD Output)
1
No External Transceivers
(Pin 50 on F65510 is ENAVDD
Output)
(Pin 48 on T65510 is ENAVDD
Output)
4
Clock Doubler Control
0 Clock doubling enabled
(CLKIN = 14.318 MHz)
1 No Clock doubling
(CLKIN = 25-50 MHz)
See also the explanation of the CLKIN input
in the Pinouts section.
7-5
Configuration bits 7-5 (CFG7-5)
Latched from MA7-5 on the falling edge (end)
of RESET and readable, but otherwise have no
hardware effect. The 65510 has internal pull-
ups on MA7-5 which are enabled only at
RESET.
The user may place external pull-
downs on MA7-5 to use these bits as Reset
configuration strap options.
Revision 0.7
CPU INTERFACE REGISTER (XR02)
Read/Write at I/O Address 3B7h/3D7h
Index 02h
D7 D6 D5 D4 D3 D2 D1 D0
0
8/16-bit CPU Memory Access
0 8-bit CPU memory access (default)
1 16-bit CPU memory access
1
Interrupt Select Control
0 Pin 49 (T65510) or Pin 51 (F65510)
outputs ENAVEE Signal (default)
1 Pin 49 (T65510) or Pin 51 (F65510)
outputs IRQ Signal
2
Reserved
4-3
Attribute Controller Mapping
00 Write Index and Data at 3C0h. (8-bit
access only) (default - VGA mapping)
01 Write Index at 3C0h and Data at 3C1h
(8-bit or 16-bit access). Attribute flip-
flop (bit-7) is always reset in this
mode (16-bit mapping)
10 Write Index and Data at 3C0h/3C1h
(8-bit access only) (EGA mapping)
11 Reserved
5
I/O Address Decoding
0 Decode all 16 bits of I/O address
(default)
1 Decode only lower 10 bits of I/O
address. This affects the following
addresses: 3B4h, 3B5h, 3B8h, 3BAh,
3BFh, 3C0h, 3C1h, 3C2h, 3C4h,
3C5h, 3CEh, 3CFh, 3D4h, 3D5h,
3D8h, 3D9h, and 3DAh.
6
Reserved (Must be programmed to 0 )
7
Attribute Flip-flop Status (read only)
0 = Index, 1 = Data
75
Extension Registers
Enable 16-bit Mem Access
Interrupt Select Control
Reserved
Attribute Controller
Mapping
10-Bit I/O Address Decode
Reserved
Attribute FF Status (R/O)
Preliminary 65510