F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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MEMORY CONTROL REGISTER

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MEMORY CONTROL REGISTER (XR04)
Read/Write at I/O Address 3B7h/3D7h
Index 04h
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Memory Wraparound Ctrl
Reserved
Control Signal Generation
Write Buffer Enable
Reserved
Reserved
1-0
Reserved (Must be programmed to 01)
2
Memory Wraparound Control
This bit enables bit-16 of the CRT Controller
address counter (default = 0 on reset).
0 Disable CRTC address counter bit-16
1 Enable CRTC address counter bit-16
3
Reserved (Must be programmed to 0)
4
Control Signal Generation Select
0 2 CAS/, 1 WE/ 256Kx16 Memory
Device
1 2 WE/, 1 CAS/ 256Kx16 Memory
Device
5
CPU Memory Write Buffer
0 Disable CPU memory write buffer
(default)
1 Enable CPU memory write buffer
6
Reserved
7
Reserved
Revision 0.7
PALETTE CONTROL REGISTER (XR06)
Read/Write at I/O Address 3B7h/3D7h
Index 06h
D7 D6 D5 D4 D3 D2 D1 D0
0
Reserved (Must be programmed to 0)
1
Reserved (Must be programmed to 0)
2
Reserved (Must be programmed to 0)
3
Reserved (Must be programmed to 0)
4
Reserved (Must be programmed to 1)
5
Bypass Internal Palette (Test Mode only)
This is a test bit and should not be set. This
feature is necessary for testing the FRC
logic.
0 Use internal Palette. Internal palette
output consists of 6 bits/pixel. Default
on reset.
1 Bypass internal Palette. The input to
the FRC logic consists of the least
significant 6 bits of the 8-bit video
data.
7-6
Color Reduction Select
These bits are effective in flat panel mode.
These bits select the algorithm used to
reduce 18-bit palette color data to 6-bit color
data for monochrome panels.
00 NTSC weighting algorithm (default)
01 Equivalent weighting algorithm
10 Green only
11 Reserved
76
Extension Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Bypass Internal Palette
FP Color Reduction Select
Preliminary 65510