F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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®
CPU PAGING REGISTER (XR0B)
Read/Write at I/O Address 3B7h/3D7h
Index 0Bh
D7 D6 D5 D4 D3 D2 D1 D0
Memory Mapping Mode
Single/Dual Map
CPU Address divide by 4
Reserved
Linear Addressing
Reserved
0
Memory Mapping Mode
0 Normal Mode (VGA compatible)
(default on Reset)
1 Extended Mode (mapping for > 256
KByte memory configurations)
1
CPU Single/Dual Mapping
0 CPU uses only a single map to access
the extended video memory space
(default on Reset)
1 CPU uses two maps to access the
extended video memory space. The
base addresses for the two maps are
defined in the Low Map Register
(XR10) and High Map Register
(XR11).
2
CPU address Divide by 4
0 Disable divide by 4 for CPU
addresses (default on Reset)
1 Enable
divide
addresses.
This allows the video
memory to be accessed sequentially in
mode 13.
In addition, all video
memory is available in mode 13 by
setting this bit.
3
Reserved
4
Linear Addressing
0 Standard VGA (A0000 - BFFFF)
memory space decoded on-chip using
A17-19 (default on Reset)
1 Linear Addressing (0.5 MB using A0-
18)
7-5
Reserved (0)
Revision 0.7
START ADDRESS TOP REGISTER (XR0C)
Read/Write at I/O Address 3B7h/3D7h
Index 0Ch
D7 D6 D5 D4 D3 D2 D1 D0
0
7-1
by
4
for
CPU
77
Extension Registers
Start Address Top
Reserved
Start Address Top
This bit defines the high order bit for the
Display Start Address when 512 KBytes of
memory is used.
Reserved (Must be programmed to 0)
Preliminary 65510