F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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DEFAULT VIDEO REGISTER (XR2B)
Read/Write at I/O Address 3B7h/3D7h
Index 2Bh
D7 D6 D5 D4 D3 D2 D1 D0
Color displayed when
screen is blanked
This register affects all modes when the screen is not
blanked and XR28 bit-2 = 1. This register effects
flat panel operation when the screen is blanked
independent of XR28 bit-2. Screen blank occurs
when SR01 bit-5 is set in any emulation mode, or
when bit-3 of the CGA / Hercules Mode Control
Register (3B8h/3D8h) is reset in CGA / Hercules
mode.
Note: For flat panel, video data output during
screen blank is different than video data
output during Panel Off power-saving
mode. In Panel Off power-saving mode,
video data is forced low or high or 3-stated
(see XR52, XR61 bit-7, and XR63 bit-7).
In Standby power saving mode, video data
is 3-stated.
7-0
Default Video
When the screen is not blanked, these bits
specify the color to be displayed during FP
blank time when XR28 bit-2 = 1. When the
screen is blanked, these bits specify the color
to be displayed for both flat panel.
Note: In flat panel mode, video data is forced to
default video before the internal RAMDAC
palette and before the FRC logic.
Revision 0.7
FP VSYNC (FLM) DELAY REGISTER (XR2C)
Read/Write at I/O Address 3B7h/3D7h
Index 2Ch
D7 D6 D5 D4 D3 D2 D1 D0
This register is used only when XR2F bit-7=0. The
First Line Marker (FLM) signal is generated from
an internal FP Vsync active edge with a delay
specified by this register. The FLM pulse width is
always one line for SS panels and two lines for
DS/DD panels.
7-0
FP VSync Delay (VDelay)
These bits define the number of Hsyncs
between the internal Vsync and the rising
edge of FLM.
88
Extension Registers
FP Vsync Delay
Preliminary 65510