F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 93/154:

FP HSYNC

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FP HSYNC (LP) DELAY REGISTER (XR2D)
Read/Write at I/O Address 3B7h/3D7h
Index 2Dh
D7 D6 D5 D4 D3 D2 D1 D0
LP Delay
(graphics mode horizontal
compression disabled )
This register is used only in flat panel mode when
XR2F bit-6 = 0 and graphics mode horizontal
compression is disabled. The LP output is generated
from the FP Blank inactive edge with a delay
specified by XR2F bit-5 and the value in this
register. The LP pulse width is specified in register
XR2F.
7-0
FP HSync (LP) Delay (HDelay)
These bits define the number of character
clocks between the FP Blank inactive edge
and the rising edge of the LP output in flat
panel mode with graphics mode horizontal
compression disabled. The msb (bit 8) of
this parameter is XR2F bit-5.
Programmed Value = Actual Value – 1
Revision 0.7
FP HSYNC (LP) WIDTH REGISTER (XR2F)
Read/Write at I/O Address 3B7h/3D7h
Index 2Fh
D7 D6 D5 D4 D3 D2 D1 D0
This register together with XR2D defines the LP
output pulse.
3-0
FP HSync (LP) Width (HWidth)
These bits define the width of LP output
pulse in terms of number of character (8-dot
only) clocks.
Programmed Value = Actual Value – 1
4
Reserved
5
FP HSync (LP) Delay (XR2D) Bit 8
This bit is the msb of the FP HSync (LP)
Delay parameter for graphics mode with
horizontal compression disabled.
6
FP HSync (LP) Delay Disable
0 FP HSync (LP) Delay Enable: XR2D
and XR2F bit-5 are used to delay the
FP HSync (LP) active edge with
respect to the FP Blank inactive edge.
1 FP HSync (LP) Delay Disable: FP
HSync (LP) active edge will coincide
with the FP Blank inactive edge.
7
FP VSync (FLM) Delay Disable
0 FP VSync (FLM) Delay Enable:
XR2C is used to delay the external FP
VSync (FLM) active edge with
respect to the internal FP VSync active
edge.
1 FP VSync (FLM) Delay Disable: the
external FP VSync (FLM) active edge
will coincide with the internal FP
VSync (FLM) active edge.
89
Extension Registers
LP Width
Reserved
LP Delay (XR2D) Bit-8
LP Delay Disable
FLM Delay Disable
Preliminary 65510