F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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PANEL FORMAT REGISTER

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PANEL FORMAT REGISTER (XR50)
Read/Write at I/O Address 3B7h/3D7h
Index 50h
D7 D6 D5 D4 D3 D2 D1 D0
Frame Rate Control
Dither Enable
Clock Divide
PWM / FRC Control
1-0
Frame Rate Control (FRC)
If bit-6 of this register is 0, these bits
specify grayscale simulation on a frame by
frame basis on monochrome flat panels
that do not support gray levels internally.
00 8-frame FRC:
simulation without dithering or 32-
level
grayscale
dithering.
01 16-frame FRC:
simulation with or without dithering.
10 4-frame FRC:
simulation without dithering or 16-
level
grayscale
dithering.
11 See description for bits 7-6.
3-2
Dither Enable
00 Disable dithering
01 Enable dithering only for 256-color
mode (AR10 bit-6 = 1)
10 Enable dithering for all modes
11 Reserved
5-4
Clock Divide (CD)
These bits specify the frequency ratio
between the dot clock and the flat panel shift
clock (SHFCLK) signal.
00 Shift Clock Freq = Dot Clock Freq
This setting is used to output 1 pixel
per shift clock with a maximum of 6
bpp (bits/pixel) for single drive
monochrome panels. This setting
cannot be used for double drive (DD)
panels. FRC and Dithering can be
enabled.
Revision 0.7
7-6
9-level grayscale
simulation
with
16-level grayscale
5-level grayscale
simulation
with
91
Extension Registers
01 Shift Clk Freq = 1/2 Dot Clock Freq
This setting is used to output 2 pixels
per shift clock with a maximum of 4
bpp (bits/pixel) for single drive
monochrome panels.
dithering can be enabled.
10 Shift Clk Freq = 1/4 Dot Clock Freq
This setting is used to output 4 pixels
per shift clock with a maximum of 2
bpp for single drive mono panels.
FRC and dithering can be enabled.
11 Shift Clk Freq = 1/8 Dot Clock Freq
This setting is used to output 8 pixels
per shift clock with a maximum of 1
bpp for single drive mono panels and
is used to output 8 pixels per shift
clock with 1 bpp for mono double
drive (DD) panels. FRC and dithering
can be enabled.
PWM / FRC Control
00 CD=00: 6 bpp PWM (dither bits 1,0)
CD=01: 4 bpp PWM (dither bits 1,0)
CD=10: 2 bpp PWM (dither bits 3,2)
CD=11: 1 bpp PWM (dither bits 5,4)
01 3 Bits/Pixel PWM (dither bits 2,1)
use only CD=00 & 01 for mono
panels
10 Reserved
11 Reserved
To use settings 01, 10, or 11 above, bits 1-0
of this register must be set to 11. In other
words, if bits 1-0 are not 11 then bits 7-6
must be programmed to 00.
Preliminary 65510
FRC and