F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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FP INTERFACE REGISTER (XR54)
Read/Write at I/O Address 3B7h/3D7h
Index 54h
D7 D6 D5 D4 D3 D2 D1 D0
FP Blank Polarity
FP Blank Select
Clock Divide
Reserved
FP LP Polarity
FP FLM Polarity
0
FP Blank Polarity
This bit controls the polarity of the
BLANK/ pin in flat panel mode.
0 Positive polarity
1 Negative polarity
1
FP Blank Select
This bit controls the BLANK/ pin output in
flat panel mode.
This bit also affects
operation of the flat panel video logic,
generation of the FP HSync (LP) pulse
signals, and masking of the Shift Clock.
0 The BLANK/ pin outputs both FP
Vertical and Horizontal Blank.
480-line DD panels, this option will
generate exactly 240 FP HSync (LP)
pulses.
1 The BLANK/ pin outputs only FP
Horizontal
Blank.
Vertical Blank, the flat panel video
logic will be active, the FP HSync
(LP) pulse will be generated, and
Shift Clock can not be masked. Note
however that Shift Clock can still be
masked during FP Horizontal Blank.
Note: The signal polarity selected by bit-0
is applicable for either selection.
Revision 0.7
4-2
Clock Divider Select Bits
These bits control the internal Dot Clock
generation from the CLKIN input. Bits 4-
2 control the divide for CLKIN to generate
the Dot Clock.
schemes are shown below:
4 3 2 DCLK
0 0 0 CLKIN
0 0 1 15/16 (CLKIN)
0 1 0 14/16 (CLKIN)
0 1 1 13/16 (CLKIN)
1 0 0 12/16 (CLKIN)
1 0 1 11/16 (CLKIN)
1 1 0 10/16 (CLKIN)
1 1 1 9/16 (CLKIN)
5
Reserved
6
FP HSync (LP) Polarity
This bit controls the polarity of the flat
panel HSync (LP) pin.
0 Positive polarity
1 Negative polarity
7
FP VSync (FLM) Polarity
This bit controls the polarity of the flat
panel VSync (FLM) pin.
0 Positive polarity
In
1 Negative polarity
During
FP
94
Extension Registers
The various divide
Preliminary 65510