FDC37C682 Standard Microsystems, FDC37C682 Datasheet
FDC37C682
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FDC37C682 Summary of contents
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Pin Enhanced Super I/O Controller Supporting 5 Volt Operation PC98/99 and ACPI Compliant SMI Support Intelligent Auto Power Management 2.88MB Super I/O Floppy Disk Controller - Relocatable to 480 Different Addresses - 15 IRQ Options (using Serial IRQ) - ...
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... The FDC37C68x is software and register compatible with SMSC's proprietary 82077AA core. IBM, PC/XT and PC/AT are registered trademarks and PS trademark The of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation 2 '95. Through internal registers, each ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION .................................................................................................................2 PIN CONFIGURATION.......................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS .................................................................................................5 FUNCTIONAL DESCRIPTION..........................................................................................................13 SUPER I/O REGISTERS ..................................................................................................................13 HOST PROCESSOR INTERFACE....................................................................................................13 FLOPPY DISK CONTROLLER .........................................................................................................15 FDC INTERNAL REGISTERS...........................................................................................................15 INSTRUCTION SET .........................................................................................................................42 SERIAL PORT (UART).....................................................................................................................69 INFRARED INTERFACE ..................................................................................................................83 PARALLEL PORT............................................................................................................................84 IBM ...
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PD3 104 PD2 105 PD1 106 PD0 107 VCC nSLCTIN 108 nINIT 109 nERROR 110 nALF 111 nSTROBE 112 RXD1 113 TXD1 114 nDSR1 115 nRTS1/SYSOPT 116 nCTS1 117 nDTR1 118 nRI1 119 nDCD1 120 RXD2 121 TXD2 122 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NAME NO./QFP PROCESSOR/HOST INTERFACE 48:55 System Data Bus 30:42, System Address Bus 22:24 46 Address Enable (DMA master has bus control) 64 I/O Channel Ready 56 Reset Drive 58,60, DMA Requests 62 57,59, DMA Acknowledge ...
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DESCRIPTION OF PIN FUNCTIONS PIN NAME NO./QFP 11 Write Disk Data 13 Head Select (1 = side Step Direction (1 = out ) 10 Step Pulse 18 Disk Change 5,6 Drive Select Lines 7,4 Motor On Lines ...
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DESCRIPTION OF PIN FUNCTIONS PIN NAME NO./QFP 127 Ring Indicator 2 (Note 2) PARALLEL PORT INTERFACE 106:99 Parallel Port Data Bus 108 Printer Select 109 Initiate Output 111 Auto Line Feed 112 Strobe Signal 96 Busy Signal 97 Acknowledge Handshake ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO./QFP I/O; (Note I/O; (Note I/O; 8042 P21 (Note I/O; Power LED Output (Note2 I/O; WDT (Note ...
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Description of Multifunction Pins with GPI/O and Other Alternate Functions PIN NO./ Original Alternate Function Function 1 QFP 19 GPIO GPI/O 70 GPI/O IRQ in 71 GPI/O IRQ in WDT Timer 72 GPI/O Output/ IRRX Power LED 73 GPI/O Output/ ...
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PIN NO./ Original Alternate Function Function 1 QFP 128 nDCD2 GPI/O 121 RXD2 GPI/O 122 TXD2 GPI/O 123 nDSR2 GPI/O 124 nRTS2 GPI/O 125 nCTS2 GPI/O 126 nDTR2 GPI/O Note (1):These pins are input (high-z) until programmed for second serial ...
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Buffer Type Descriptions I Input, TTL compatible. IS Input with Schmitt trigger. I/OD16P Input/Output, 16mA sink, 90uA pull-up. I/O24 Input/Output, 24mA sink, 12mA source. I/O4 Input/Output, 4mA sink, 2mA source. O4 Output, 4mA sink, 2mA source. O16SR Output, 16mA sink, ...
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SMI MANAGEMENT ADDRESS BUS SERIRQ SERIAL IRQ PCICLK nIOR nIOW AEN SA[0:15] HOST SD[O:7] CPU INTERFACE DRQ[A-C] nDACK[A-C] TC RESET_DRV CLOCK GEN IOCHRDY nINDEX nTRK0 nDSKCHG nWRPRT Vcc Vss CLKIN nWGATE (14.318) HCLK 14CLK (14.318) FDC37C68x BLOCK DIAGRAM nGPA ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, and auxiliary I/O can ...
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LOGICAL LOGICAL REGISTER DEVICE DEVICE INDEX NUMBER 0x04 Serial Port 1 0x60,0x61 0x05 Serial Port 2 0x60,0x61 0x07 KYBD N/A 0x08 Aux. I/O 0x60,0x61 0x62,0x63 BASE I/O RANGE FIXED BASE (NOTE 3) OFFSETS [0x100:0xFF8 RB/TBILSB div +1 : ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR and several disk PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the direction ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 Active ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These two ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC does not characteristics modified for tape support. The contents of this register are not used internal ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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Table 9 - Drive Type ID Digital Output Register Bit 1 Bit Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. Register 3F3 - Drive Type ID Bit 5 ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 13 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns 26 ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can RQM DIO NON DMA BIT DRV ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check ...
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Table 16 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 17 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Indicates the status of the WP pin Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: ...
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PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. ...
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Execution Phase All data transfers to or from the FDC during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred ...
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FIFO has <threshold> bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 19 - Description of Command Symbols SYMBOL NAME EOT End of Track GAP GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector N Sector Size Code ...
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Table 19 - Description of Command Symbols SYMBOL NAME ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative Cylinder Number SC Number of Sectors Per Track ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 20 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 -------- ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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54 ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 24 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 27 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The ...
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NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done four drives at once. ...
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Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the ...
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EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers ...
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It is the user's responsibility to compensate FDC functions (precompensation track number) accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). ...
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown on page ...
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Table 30 - Effects of WGATE and GAP Bits WGATE GAP LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO Command has ...
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The FDC37C68x incorporates two full function UARTs. They are compatible NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-to- parallel conversion on received characters and parallel-to-serial conversion characters. The data rates are independently programmable from 460.8K baud ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writting to this bit ...
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Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT BIT BIT BIT PRIORIT LEVEL Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit ...
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The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This ...
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: -Bit 0=1 as long as there is one byte in the RCVR FIFO. -Bits 1 ...
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Table 34 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write Only) DLAB = 0 ADDR = 1 Interrupt ...
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Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Receiver Enable MODEM 0 Line Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use ...
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The FDC37C68x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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Table 36 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI- DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. DATA PORT 0 for a description of operation. This register is only available in EPP mode. ...
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Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. 6. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of ...
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In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error Note 1: SPP and EPP can use 1 common register. ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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D7 D6 data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 0 0 cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB compress intrValue ecr MODE Note 1: These registers are available in all modes. Note 2: All FIFOs use one common ...
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Table 38 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition Table 39 - ECP Register Definitions NAME ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...
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ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read low level. This means that this chip does not support hardware RLE compression. support hardware de-compression! BIT 6 intrValue ...
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Table 41A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in ...
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This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. The interrupt generated is ISA friendly ...
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DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. enabled directly by asserting nPDACK and addresses need not be valid. ...
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The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO this time the FIFO is full, it can be completely ...
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PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. ...
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CHIP PIN # SPP MODE CONNECTOR PIN # 1 112 2 106 3 105 4 104 5 103 6 102 7 101 8 100 111 15 110 nERROR 16 ...
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AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management ...
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Register Behavior Table 43 reiterates the AT and PS/2 (including Model 30) configuration registers available. It also shows the type of access permitted. order to maintain software transparency, access to all the registers must be maintained. Table 43 shows, two ...
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Table 43 - PC/AT and PS/2 Available Registers Base + Address Available Registers PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins nRDATA ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23- B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter ...
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Functions The second alternate function for pins 113-118 are the 8042 functions P12-P17. These are implemented true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. ...
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GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION The FDC37C68x provides a set of flexible Input/Output control functions to the system designer through a set of General Purpose I/O pins (GPI/O). These GPI/O pins may perform simple I/O or may be individually configured ...
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The FDC37C68x also has 13 GPI/O ports that are the first alternate functions of pins with other default functions. These pins are listed in Table 46B below. Table 46B - Multifunction GPI/O Pins Pin Original Number Function 19 GPIO 85 ...
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GPI/O registers GP1 through GP4, GP6 and 7, as well as WDT2_VAL and SMI Enable and Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses an ...
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Table 47B - Index and Data Register Normal (Run) Mode INDEX NORMAL (RUN) MODE 0x01 Access to GP1 (L8 - CRF6) 0x02 Access to GP2 (L8 - CRF7) 0x03 Access to Watchdog Timer Control (L8 - CRF4) 0x04 Access to ...
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GPI/O ports contain alternate functions which are either output-type or input-type. The GPI/O port structure for each SD-bit D-TYPE nIOW Transparent nIOR GPI/O GPIO Register Configuration Bit-n Register bit-3 (Alt Function) Alternate Input Function GPI/O having an input-type alternate function. ...
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GPIO Configuration Register bit-3 (Alt Function) Alternate Output Function SD-bit D-TYPE nIOW 0 Transparent 1 nIOR GPI/O Register Bit-n GPI/O having an output-type alternate function. [GP12--GP17, GP20, GP22--GP25] GPI/O GPI/O Configuration Configuration Register bit-1 Register bit-0 (Input/Output) (Polarity ...
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General Purpose I/O Configuration Registers Assigned to each GPI/O port is an 8-bit GPI/O Configuration Register which independently program each I/O port. GPI/O Configuration Registers accessible when the FDC37C68x is in the Configuration Mode; more information can be found in ...
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Table 48 - GPI/O Configuration Register Bits [3:0] ALT FUNC INT EN POLARITY BIT 3 BIT 2 0=DIS- 0=DISABLE ABLE 1=ENABLE INVERT 1=SELECT 1=INVERT I/O BIT 1 BIT 0 0=NO ...
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Table 48 - GPI/O Configuration Register Bits [3:0] ALT FUNC INT EN POLARITY BIT 3 BIT 2 0=DIS- 0=DISABLE ABLE 1=ENABLE 1=SELECT 1=INVERT The alternate function of GP10 and GP11 allows these GPI/O port pins to ...
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Reading and Writing GPI/O Ports When a GPI/O port is programmed as an input, reading it through the GPI/O register latches either the inverted or non-inverted logic value present at the GPI/O pin; writing it has no Table 49 - ...
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WDT to reload the value stored in WDT_VAL and reset the WDT time-out status bit if set. If all three system events are disabled the WDT will inevitably time out. The Watch Dog Timer ...
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Table 51 - Watchdog Timer/Power LED Configuration Registers CONFIG REG. BIT FIELD WDT_VAL Bits[7:0] WDT_CFG Bit[0] Bit[1] Bit[2] Bit[3] Bits[7:4] WDT_CTRL Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] General Purpose Address Decoder General Purpose I/O pin GP14 may be configured as a ...
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GP17 Joystick Function The FDC37C68x may be configured to generate a Joystick Write Strobe on GP17. When configured as a Joystick Write Strobe the output is a decode ...
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KEYBOARD CONTROLLER FUNCTIONAL DESCRIPTION The FDC37C68x is a Super I/O and Universal Keyboard Controller that is intelligent keyboard management in desktop computer applications. The Super I/O supports a Floppy Disk Controller, two 16550 type serial ports and one ECP/EPP ...
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KEYBOARD ISA INTERFACE The FDC37C68x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status Table 52 - ISA I/O Address Map ISA ADDRESS nIOW nIOR ...
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CPU-to-Host Communication The FDC37C68x CPU can write to the Output Data register via register DBB. A write 8042 INSTRUCTION OUT DBB Set OBF, and, if enabled, the KIRQ output signal goes high Host-to-CPU Communication The host system can send both ...
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KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. ...
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Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37C68x CPU. UD Writable by FDC37C68x CPU. These bits are user-definable. C/D (Command Data)-This bit specifies whether the input data ...
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GATEA20 AND KEYBOARD RESET The FDC37C68x provides two options for GateA20 and Keyboard Reset: 8042 Software GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 ...
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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of ...
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SYSTEM MANAGEMENT INTERRUPT (SMI) The FDC37C68x implements a group nSMI output pin. The System Management Interrupt is a non- maskable interrupt with the highest priority level used for transparent power management. The nSMI group interrupt output consists of the enabled ...
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A new feature added which will prevent a hung system from having to be unplugged. This new feature functions as follows: When the chip generates an nSMI via the SMI IRQ routing registers from any block including ...
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SERIAL INTERRUPTS MSIO will support the serial interrupt scheme, which is adopted by several companies, to transmit interrupt information to the system. Specification for PCI Systems” Version 6.0. Timing Diagrams For IRQSER Cycle PCICLK = 33Mhz_IN pin IRQSER = SERIRQ ...
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Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2) There may be none, one or more Idle states during the Stop Frame. 3) The next IRQSER cycle’s Start Frame pulse may or ...
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The FDC37C68x will drive the IRQSER line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition ...
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Latency Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data Frames of seventeen, will range clocks (3.84uS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one ...
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The Configuration of the FDC37C68x is very flexible and is based on the configuration architecture implemented in typical Plug-and- Play components. The FDC37C68x is designed for motherboard applications in which the resources required by their components are known. With its ...
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To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip Configuration State the Config Key is sent to the ...
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Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 56 - Configuration Registers HARD ...
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Table 56 - Configuration Registers HARD RESET INDEX TYPE / Vcc POR 0xF1 R/W 0x00 0xF2 R/W 0xFF 0xF4 R/W 0x00 0xF5 R/W 0x00 LOGICAL DEVICE 1 CONFIGURATION REGISTERS RESERVED LOGICAL DEVICE 2 CONFIGURATION REGISTERS RESERVED LOGICAL DEVICE 3 CONFIGURATION ...
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Table 56 - Configuration Registers HARD RESET INDEX TYPE / Vcc POR 0x72 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x62, R/W 0x00, 0x63 0x00 0xB0 R/W ...
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Table 56 - Configuration Registers HARD RESET INDEX TYPE / Vcc POR 0xE2 R/W - 0xE3 R/W - 0xE4 R/W - 0xE5 R/W - 0xE6 R/W - 0xE7 R/W - 0xE8 R/W - 0xE9 R/W - 0xEA R/W - 0xEB ...
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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and REGISTER ADDRESS 0x00 - 0x01 Config Control ...
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REGISTER ADDRESS Reset_Drv Card Level 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Reserved Device ID 0x20 R Hard wired = 0x48 Device Rev 0x21 R Hard wired = 0x01 PowerControl 0x22 R/W Default = 0x00. on ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04, on Vcc POR or Reset_Drv hardware signal. Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= Vcc POR or Reset_Drv Configuration ...
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REGISTER ADDRESS Clock Mask 0x28 Register Default = 0x00 on VCC POR and Hard Reset Chip Level 0x29 -0x2B Reserved - Writes are ignored, reads return 0. Vendor Defined TEST 4 0x2C R/W TEST 1 0x2D R/W TEST 2 0x2E ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports six logical units and has six sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1 ...
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Table 58 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,072) Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 on ...
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Table 59 - I/O Base Address Configuration Register Description LOGICAL LOGICAL REGISTER DEVICE DEVICE INDEX NUMBER 0x00 FDC 0x60,0x61 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 0x07 KYBD n/a BASE I/O RANGE (NOTE3) ...
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Table 59 - I/O Base Address Configuration Register Description LOGICAL LOGICAL REGISTER DEVICE DEVICE INDEX NUMBER 0x08 Aux. I/O 0x60,0x61 0x62,0x63 Note: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. ...
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Table 60 - Interrupt Select Configuration Register Description NAME REG INDEX Interrupt 0x70 (R/W) Request Level Select 0 Default = 0x00 on Vcc POR or Reset_Drv Note: An Interrupt is activated by setting the Interrupt Request Level Select 0 register ...
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IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Configuration Table 62 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Mode Register 0xF0 R/W Default = 0x0E on Vcc POR or ...
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Table 62 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Type Register 0xF2 R/W Default = 0xFF on Vcc POR or Reset_Drv 0xF3 R FDD0 0xF4 R/W Default = 0x00 on Vcc ...
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Table 63 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on Vcc POR or Reset_Drv PP Mode Register 2 0xF1 R/W Default = 0x00 on Vcc ...
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Table 64 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: To properly share and IRQ, 1. ...
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Table 65 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on Vcc POR or Reset_Drv IR Half Duplex 0xF2 Timeout Default = 0x03 on Vcc ...
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Reserved, Logical Device 6 [Logical Device Number = 0x06] Table 66 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF Table 67 ...
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Table 67 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX SMI Enable 0xB5 R/W Register 2 (Note 1) Default = 0x00 on VCC POR SMI Status 0xB6 R/W Register 1 (Note 1) Default = ...
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Table 67 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX SMI Status 0xB7 R/W Register 2 (Note 1) Default = 0x00 on VCC POR Note 1: WDT2_VAL, SMI enable and Status Registers are also ...
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Unless otherwise noted, the Definition for the GP Registers below all have the following form: Bit[0] In/Out: =1 Input, =0 Output Bit[1] Polarity: =1 Invert Invert Bit[2] Int Enable Combined IRQ 1 =0 Disable Combined ...
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Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX 0xC0-0xC6 GP47 0xC7 Default = 0x01 on VCC POR 0xC8-0xCF GP60 0xD0 Default = 0x01 on VCC POR GP61 0xD1 Default = 0x01 ...
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Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP65 0xD5 Default = 0x01 on VCC POR GP66 0xD6 Default = 0x01 on VCC POR GP67 0xD7 Default = 0x01 on VCC ...
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Table 67 (cont’d) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP74 0xDC Default = 0x01 on VCC POR GP75 0xDD Default = 0x01 on VCC POR GP76 0xDE Default = 0x01 on VCC ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP10 0xE0 Default = 0x01 on VCC POR GP11 0xE1 Default = 0x01 on VCC POR DEFINITION General Purpose I/0 bit 1.0 Bit[0] In/Out ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP12 0xE2 Default = 0x01 on VCC POR GP13 0xE3 Default = 0x01 on VCC POR GP14 0xE4 Default = 0x01 on VCC POR ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP16 0xE6 Default = 0x01 on VCC POR GP17 0xE7 Default = 0x01 on VCC POR GP20 0xE8 Default = 0x01 on VCC POR ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Default = 0x01 on VCC POR GP22 0xEA Default = 0x01 on VCC POR GP23 0xEB Default = 0x01 on VCC POR GP24 0xEC ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX 0xEE GP_INT2 0xEF Default = 0x00 on VCC POR GP_INT1 0xF0 Default = 0x00 on VCC POR GPA_GPW_EN 0xF1 Default = 0x00 on Vcc ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Default = 0x00 on Vcc POR or Reset_Drv WDT_CFG 0xF3 Default = 0x00 on Vcc POR or Reset_Drv WDT_CTRL 0xF4 (Note 1) Default = ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP1 (Note 1) 0xF6 Default = 0x00 on Vcc POR or Reset_Drv GP2 (Note 1) 0xF7 Default = 0x00 on Vcc POR or Reset_Drv ...
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Table 68 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Default = 0x00 on Vcc POR or Reset_Drv GP7 (Note 1) 0xFB Default = 0x00 on Vcc POR or Reset_Drv Note1: Registers GP1-2, WDT_CTRL, ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage O20 Type Buffer Low Output Level High Output Level Output Leakage O24 Type Buffer ...
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PARAMETER SYMBOL OD16P Type Buffer Low Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR) Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) Suppy Current Active Note 1: All output leakages are ...
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CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance = 5V CC LIMITS MIN TYP MAX OUT 179 UNIT TEST CONDITION pF ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used. NAME SD[0:7] IOCHRDY SERIRQ DRQ[0:3] HCLK 14CLK nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT ...
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NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to 4.5V t3 All Host Accesses ...
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AEN t3 SA[x] t1 nIOW SD[x] GP I/O FINTR PINTR IBF NAME DESCRIPTION t1 SA[x] and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], invalid t4 SD[x] Valid to nIOW deasserted t5 ...
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AEN SA[x] t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW SEE TIMING PARAMETERS ON NEXT PAGE DATA VALID t9 t8 FIGURE 3 - ISA READ 183 t13 t6 t5 t10 ...
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NAME DESCRIPTION t1 SA[x] and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x] invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from nIOR deasserted t6 nIOR deasserted t8 nIOR asserted ...
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PCOBF AUXOBF1 nWRT IBF nRD FIGURE 4 - INTERNAL 8042 CPU TIMING NAME DESCRIPTION t1 nWRT deasserted to AUXOBF1 asserted (Notes 1,2) t2 nWRT deasserted to PCOBF asserted (Notes 1,3) t3 nRD deasserted to IBF deasserted (Note 1) Note 1: ...
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X1K FIGURE 5A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz Clock Rise Time/Fall Time (not shown) RESET NAME DESCRIPTION t4 RESET width (Note 1) Note 1: The RESET ...
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AEN FDRQ, PDRQ nDACK t14 nIOR or nIOW DATA (DO-D7) TC FIGURE 6A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay ...
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AEN FDRQ, PDRQ t1 nDACK t14 t11 t6 t5 nIOR or nIOW DATA (DO-D7) TC FIGURE 6B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW ...
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MTR0-1 FIGURE 7 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 8 - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from ...
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...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR FIGURE 10 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t12 ...
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EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) t5 nWAIT Asserted ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 11 - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t11 ...
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EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t6 t19 t12 t11 ...
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EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted to PDATA Invalid ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t15 t11 t13 t12 t10 t5 t2 198 t22 ...
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EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted to IOCHRDY Asserted ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500Kbytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer ...