ADSP2171 Analog Devices, ADSP2171 Datasheet
ADSP2171
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ADSP2171 Summary of contents
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... The ADSP-2173 is designed for 3.3 V applications. The ADSP-2172 also has 8K words (24-bit) of program ROM. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use ...
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... Evaluation Board plug-in card, but it can operate in stand-alone mode. The evaluation board/system de- velopment board executes EPROM-based or downloaded pro- grams. Modular Analog Front End daughter cards with different codecs will be made available. EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc. INSTRUCTION REGISTER DATA DATA ...
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... The HIP is extremely flexible and provides a simple inter- face to a variety of host processors. For example, the Motorola 68000 series, the Intel 80C51 series and the Analog Devices’ ADSP-2101 can be easily connected to the HIP. The host pro- cessor can initialize the ASDP-217x’s on-chip memory through the HIP ...
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ADSP-2171/ADSP-2172/ADSP-2173 Pin Description The ADSP-217x is available in 128-lead TQFP and 128-lead PQFP packages. Table I contains the pin descriptions. Table I. ADSP-217x Pin List Pin # Group of Input/ Name Pins Output Function Address 14 O Address output for ...
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Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-217x provides up to three external interrupt input pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi- ...
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ADSP-2171/ADSP-2172/ADSP-2173 LOW POWER OPERATION The ADSP-217x has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: Powerdown Idle Slow Idle The CLKOUT pin may also be disabled to reduce ...
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CLOCK OR CRYSTAL CLKIN XTAL PWD PWDACK CLKOUT RESET IRQ2 BR BG MMAP 3 FL2-0 PMS PROGRAM OE MEMORY WE (OPTIONAL) NOTE: THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF ...
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ADSP-2171/ADSP-2172/ADSP-2173 Program Memory Interface The on-chip program memory address bus (PMA) and the on- chip program memory data bus (PMD) are multiplexed with on-chip DMA and DMD buses, creating a single external data bus and a single external address bus. ...
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... ROM NRE Agreement & Minimum Quantity Order (MQO) Acceptance Agreement for Pre-production ROM Products. 2. Return the forms to Analog Devices along with two copies of the Memory Image File (.EXE file) of your ROM code. The files must be supplied on two 3.5" or 5.25" floppy disks for IBM PC (DOS 2 ...
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ADSP-2171/ADSP-2172/ADSP-2173 Bus Request & Bus Grant The ADSP-217x can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-217x is ...
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ASTAT ALU Result Zero AN ALU Result Negative AV ALU Overflow AC ALU Carry AS ALU X Input Sign AQ ALU Quotient MV ...
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ADSP-2171/ADSP-2172/ADSP-2173 DWAIT4 SPORT0 Multichannel Receive Word Enable Registers 1 = Channel Enabled 0 = Channel Ignored 0x3FFA ...
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CLKODIS CLKOUT Disable Control Bit BIASRND MAC Biased Rounding Control Bit TIREG Transmit Autobuffer I Register TMREG Transmit Autobuffer M ...
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ADSP-2171/ADSP-2172/ADSP-2173 SPORT1 SCLKDIV Serial Clock Divide Modulus 0x3FF1 XTALDIS XTAL Pin Drive Disable during Powerdown 1 = disabled enabled (disable XTAL ...
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HDR5 Write 2171 HDR4 Write 2171 HDR3 Write 2171 HDR2 Write 2171 HDR1 Write 2171 HDR0 Write Overwrite Mode Software Reset Biased ...
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ADSP-2171/ADSP-2172/ADSP-2173 Example Code The following example is a code fragment that performs the filter tap update for an adaptive (least-mean-squared algorithm) filter. Notice that the computations in the instructions are written like algebraic equations. MF=MX0*MY1 (RND), MX0=DM (I2,M1); /* MF=error*beta ...
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ADSP-2171/ADSP-2172–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Hi-Level RESET Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 * ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0 Input ...
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ADSP-2171/ADSP-2172 Parameter Clock Signals t is defined as 0.5 t The ADSP-2171/ADSP-2172 uses an CK CKI. input clock with a frequency equal to half the instruction rate; a clock (which is equivalent to 60 ns) yields processor ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Interrupts and Flags Timing Requirement: t IRQx or FI Setup before CLKOUT Low IFS t IRQx or FI Hold after CLKOUT High IFH Switching Characteristic: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay ...
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ADSP-2171/ADSP-2172 Parameter Bus Request/Grant Timing Requirement Hold after CLKOUT High Setup before CLKOUT Low BS Switching Characteristic: t CLKOUT High to DMS, PMS, BMS, SD RD, WR Disable t DMS, PMS, BMS, RD, WR SDB ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Memory Read Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High ...
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ADSP-2171/ADSP-2172 Parameter Memory Write Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before WR Low ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Serial Ports Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC t SCLK ...
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ADSP-2171/ADSP-2172 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 0) Timing Requirement: t HA2–0 Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t HA2–0, HRW Setup before Start of Write or Read HSU t Data Setup before End of ...
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ADSP-2171/ADSP-2172 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 0) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup, before ALE Low HASU t HAD15–0 Address Hold after ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup before ALE Low HASU t HAD15–0 Address Hold ...
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ADSP-2171/ADSP-2172 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – (PD ) AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 CAPACITIVE LOADING Figures 19 and 20 show the capacitive loading characteristics of the ADSP-2171/ADSP-2172 4. 100 C – Figure 19. Typical Output Rise ...
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ADSP-2173–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Hi-Level RESET Voltage Lo-Level Input Voltage ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 TIMING PARAMETERS GENERAL NOTES Use the exact timing information given. Do not attempt to de- rive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values ...
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ADSP-2173 Parameter Clock Signals t is defined as 0.5 t The ADSP-2173 uses an input clock with CK CKI. a frequency equal to half the instruction rate; a 10.0 MHz input clock (which is equivalent to 100 ns) yields a ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Interrupts and Flags Timing Requirement: t IRQx or FI Setup before CLKOUT Low IFS t IRQx or FI Hold after CLKOUT High IFH Switching Characteristic: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay ...
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ADSP-2173 Parameter Bus Request/Grant Timing Requirement Hold after CLKOUT High Setup before CLKOUT Low BS Switching Characteristic: t CLKOUT High to DMS, PMS, BMS, SD RD, WR Disable t DMS, PMS, BMS, RD, WR SDB ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Memory Read Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High ...
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ADSP-2173 Parameter Memory Write Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before WR Low ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Serial Ports Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC t SCLK ...
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ADSP-2173 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 0) Timing Requirement: t HA2–0 Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t HA2–0, HRW Setup before Start of Write or Read HSU t Data Setup before End of ...
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ADSP-2173 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 0) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup, before ALE Low HASU t HAD15–0 Address Hold after ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup before ALE Low HASU t HAD15–0 Address Hold ...
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ADSP-2173 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – (PD ) AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal ...
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ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 CAPACITIVE LOADING Figures 35 and 36 show the capacitive loading characteristics of the ADSP-2173 3 100 C – Figure 35. Typical Output Rise ...
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GND GND HA2/ALE HA1 HA0 HSEL HD5 HD4 HD3 HD2 HD1 HD0 V DD GND XTAL CLKIN CLKOUT GND A8 A9 A10 A11 A12 A13 NC MMAP NC ...
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ADSP-2171/ADSP-2172/ADSP-2173 TQFP Pin TQFP Number Name Number 1 GND 33 2 GND 34 3 HA2/ALE 35 4 HA1 36 5 HA0 37 6 HSEL 38 7 HD5 39 8 HD4 40 9 HD3 41 10 HD2 42 11 HD1 43 ...
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Metric Thin Plastic Quad Flatpack (TQFP) SEATING PLANE SYMBOL REV. A ADSP-2171/ADSP-2172/ADSP-2173 OUTLINE DIMENSIONS D ...
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ADSP-2171/ADSP-2172/ADSP-2173 128 1 HA2/ALE HA1 HA0 HSEL HD5 HD4 HD3 HD2 HD1 HD0 V DD GND XTAL CLKIN CLKOUT GND A8 A9 A10 A11 A12 A13 ...
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PQFP Pin PQFP Number Name Number 1 HA2/ALE 33 2 HA1 34 3 HA0 35 4 HSEL 36 5 HD5 37 6 HD4 38 7 HD3 39 8 HD2 40 9 HD1 41 10 HD0 ...
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ADSP-2171/ADSP-2172/ADSP-2173 128-Lead Metric Thin Plastic Quad Flatpack (PQFP) SEATING PLANE SYMBOL OUTLINE DIMENSIONS D ...
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Part Number** ADSP-2171KST-133 ADSP-2171BST-133 ADSP-2171KS-133 ADSP-2171BS-133 ADSP-2171KST-104 ADSP-2171BST-104 ADSP-2171KS-104 ADSP-2171BS-104 ADSP-2173BST-80 ADSP-2173BS-80 *Refer to section titled “Ordering Procedure for ADSP-2172 ROM Processors” for information about ordering ROM-coded parts. **S = Plastic Quad Flatpack Plastic Thin Quad Flatpack. REV. ...
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