AM486 Advanced Micro Systems, Inc., AM486 Datasheet
AM486
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AM486 Summary of contents
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... Wide range of chipsets supporting SMM avail- able to allow product differentiation GENERAL DESCRIPTION The Enhanced Am486 microprocessor family is an ad- dition to the Am486 microprocessor family of products. The new family enhances system performance by incor- porating a write-back cache implementation, flexible clock control, and enhanced SMM. Table 1 shows avail- able processors in the Enhanced Am486 microproces- sor family ...
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... Address Lookaside Buffer 128 Displacement Bus Prefetcher 32 32-Byte Code Stream Code Queue 2x16 Bytes Instruction 24 Decode Decoded Instruction Path Enhanced Am486 Microprocessor VOLDET Power Plane Clock Interface CLK Clock CLKMUL Generator STPCLK Bus Interface A31–A2 Address BE3–BE0 ...
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... S = 208-pin SQFP (Shrink Quad Flat Pack Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Enhanced Am486 Microprocessor AMD Valid Combinations 3 ...
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... AHOLD Bus Arbitration Implementation .................................................................... 28 4.8.5.3 Normal Write-Back ..................................................................................................... 28 4.8.6 Reordering of Write-Backs (AHOLD) with BOFF ................................................................. 29 4.8.7 Special Scenarios For AHOLD Snooping ............................................................................ 30 4.8.7.1 Write Cycle Reordering due to Buffering ................................................................... 30 4.8.7.2 BOFF Write-Back Arbitration Implementation ............................................................ 32 4.8.8 BOFF Design Considerations .............................................................................................. 32 4.8.8.1 Cache Line Fills ......................................................................................................... 32 4.8.8.2 Cache Line Copy-Backs ............................................................................................ 32 4.8.8.3 Locked Accesses ....................................................................................................... 32 4 PRELIMINARY Enhanced Am486 Microprocessor ...
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... SMRAM Interface ................................................................................................................ 48 7.8.2 Cache Flushes .................................................................................................................... 49 7.8.3 A20M Pin ............................................................................................................................. 49 7.8.4 CPU Reset during SMM ...................................................................................................... 52 7.8.5 SMM and Second Level Write Buffers ................................................................................ 52 7.8.6 Nested SMI and I/O Restart ................................................................................................ 52 7.9 SMM Software Considerations ..................................................................................................... 52 7.9.1 SMM Code Considerations ................................................................................................. 52 7.9.2 Exception Handling ............................................................................................................. 52 7.9.3 Halt during SMM .................................................................................................................. 53 7.9.4 Relocating SMRAM to an Address above 1 Mbyte ............................................................. 53 PRELIMINARY Enhanced Am486 Microprocessor AMD 5 ...
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... Using TR4 and TR5 for Cache Testing.......................................................................................... 55 8.3.1 Example 1: Reading the Cache (write-back mode only) ...................................................... 55 8.3.2 Example 2: Writing the Cache .............................................................................................. 55 8.3.3 Example 3: Flushing the Cache ........................................................................................... 55 9 Enhanced Am486 CPU Functional Differences .................................................................................. 55 9.1 Status after Reset ......................................................................................................................... 55 9.2 Cache Status ................................................................................................................................ 55 10 Enhanced Am486 CPU Identification .................................................................................................. 56 10.1 DX Register at RESET ................................................................................................................ 56 10 ...
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... I/O Trap Word Configuration ................................................................................................... 47 Table 17 Test Register (TR4) ................................................................................................................. 53 Table 18 Test Register (TR5) ................................................................................................................. 53 Table 19 CPU ID Codes ......................................................................................................................... 56 Table 20 CPUID Instruction Description ................................................................................................. 56 Table 21 Thermal Resistance (°C/W) Table 22 Maximum T at Various Airflows in °C .................................................................................... 67 A PRELIMINARY and for the Am486 CPU in 168-Pin PGA Package ......... Enhanced Am486 Microprocessor AMD 7 ...
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... VCC D3 D5 VCC D6 BE0 PWT RDY V V BE1 BE3 V V PCD Enhanced Am486 Microprocessor A31 A28 A27 A29 V A25 A26 DP0 A30 A17 V A23 CC A19 V VOLDET SS ...
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... DP0 N-3 DP1 F-1 DP2 H-3 DP3 A-5 EADS B-17 FERR C-14 FLUSH C-15 HITM A-12 HLDA P-15 HOLD E-15 IGNNE A-15 INTR A-16 INV A-10 KEN F-15 LOCK N-15 M/IO N-16 NMI B-15 PCD J-17 PCHK Q-17 PLOCK Q-16 PWT L-15 RDY F-16 RESET C-16 SMI B-10 SMIACT C-12 SRESET C-10 STPCLK G-15 UP C-11 VOLDET S-4 WB/WT B-13 W/R N-17 . Enhanced Am486 Microprocessor AMD V V Test INC cc ss Pin Pin Pin Pin No. No. No. No. A-7 A-3 A-13 B-7 A-14 C-13 B-9 A-9 B-16 J-1 B-11 A-11 B-14 C-4 B-3 C-5 B-4 E-2 B-5 E-1 E-16 G-2 E-17 G-16 G-1 H-16 G-17 K-2 H-1 K-16 H-17 L-16 K-1 M-2 K-17 M-16 L-1 P-16 L-17 R-3 M-1 R-6 M-17 R-8 P-17 R-9 Q-2 ...
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... AMD 1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package 10 PRELIMINARY TOP VIEW Enhanced Am486 Microprocessor ...
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... LOCK 207 M/IO 37 NMI 51 PCD 41 PCHK 4 PLOCK 206 PWT 40 RDY 12 RESET 48 SMI 65 SRESET 58 STPCLK 73 SMIACT 59 UP 194 WB/WT 64 W/R 27 Enhanced Am486 Microprocessor AMD Test INC Pin Pin Pin Pin No. No. No. No 168 167 127 ...
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... Interrupts RESET SRESET HOLD BREQ HLDA Bus Arbitration 12 PRELIMINARY Enhanced Am486 CPU BOFF TCK IGNNE FERR Numeric Error Reporting Enhanced Am486 Microprocessor D31–D0 Data Bus 32 DP3–DP0 4 Data Parity PCHK BRDY Burst BLAST Control CACHE SMI SMM SMIACT PWT Page ...
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... Am486DX processor. These added signals support the enhanced processor features and are indicated as “New” in the pin descrip- tion titles. Some Am486DX CPU signals have new func- tions to implement the Enhanced Am486 processor write-back cache protocol. These signals are indicated as “ ...
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... The CLK input provides the basic microprocessor timing signal. The CLKMUL input selects the multiplier value used to generate the internal operating frequency for the Enhanced Am486 microprocessor family. All exter- nal timing parameters are specified with respect to the rising edge of CLK. The clock signal passes through an internal Phase-Lock Loop (PLL) ...
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... HOLD must satisfy setup and hold times t IGNNE Ignore Numeric Error (Active Low; Input) When this pin is asserted, the Enhanced Am486 micro- processor will ignore a numeric error and continue ex- ecuting non-control floating-point instructions. When IGNNE is deasserted, the Enhanced Am486 micropro- ...
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... If SMI is asserted asynchronous- ly, it must go High for a minimum of two clocks before going Low, and it must remain Low for at least two clocks to guar- Enhanced Am486 Microprocessor and CLK have CC and ...
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... The pin uses an internal pull-up resistor. VOLDET – Voltage Detect (Output) VOLDET provides an external signal to allow the system to determine the CPU input power level ( V). For Enhanced Am486 processors, the pin ties internally WB/WT New – ...
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... Address Mode (Virtual Mode), Protected Address Mode (Protected Mode), and System Management Mode (SMM). 4.3.1 Real Mode In Real Mode, the Enhanced Am486 microprocessor operates as a fast 8086. Real Mode is required primarily to set up the processor for Protected Mode operation. 4.3.2 Virtual Mode In Virtual Mode, the processor appears Real Mode, but can use the extended memory accessing of Protected Mode ...
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... Cache Line Overview To implement the Enhanced Am486 microprocessor cache coherency protocol, each tag entry is expanded to 2 bits: S1 and S0. Each tag entry is associated with a cache line. Table 3 shows the cache line organization ...
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... Cacheability The Enhanced Am486 CPU caches data based on the state of the CD and NW bits in CR0, in conjunction with the KEN signal, at the time of a burst read access from memory. If the WB/WT signal is Low during the first ...
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... In this case, the snoop requires the use of the cycle control signals and the data bus. The following sec- tions describe the scenarios for the HOLD, AHOLD, and BOFF implementations. Enhanced Am486 Microprocessor AMD Invalid (EADS = 0 * INV = 1) + FLUSH = 0 ...
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... HOLD and HLDA control signals. These signals are then centralized to the core system logic that controls individual bus mas- ters, depending on bus request signals and the HITM signal. Enhanced Am486 Microprocessor Inputs Outputs Must be steady Will be steady ...
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... Note: The circled numbers in this figure represent the steps in section 4.8.2.2.2. CLK ADR ADS BLAST BRDY Data WB/WT BOFF Note: The circled numbers in this figure represent the steps in section 4.8.2.2.3. Enhanced Am486 Microprocessor PRELIMINARY n n n+4 Figure 4. External Read n n Figure 5. External Write AMD n+8 n+12 3 n+8 n+12 ...
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... Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line CLK ADR INV EADS HITM HOLD HLDA Note: The circled numbers in this figure represent the steps in section 4.8.3.2. Figure 7. Snoop of On-Chip Cache That Hits a Non-modified Line 24 PRELIMINARY valid valid Á À valid valid Á À Enhanced Am486 Microprocessor   ...
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... If INV is 1, snooping is caused by a write access. EADS is not sampled again until after the modified line is written back to memory detected again as early as in Step 11. n n+4 n+8 n n+4 n+8 n+12 Enhanced Am486 Microprocessor AMD floating/three-stated 11 6 valid ...
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... The micro- processor gives the write-back access priority. This implies that if HOLD is deasserted, the microprocessor first writes back the modified line (see Figure 9). n+4 n n+4 n+8 n+12 Figure 9. Write-Back and Pending Access Enhanced Am486 Microprocessor n+ valid ...
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... The status of the addressed line is now either shared (INV = changed to invalid (INV = 1). 4.8.5.1 HOLD/HLDA Write-Back Design Considerations When designing a write-back cache system that uses HOLD/HLDA as the bus arbitration method, the follow- ing considerations must be observed to ensure proper operation (see Figure 10). Valid Hold Assertion Enhanced Am486 Microprocessor AMD 27 ...
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... Address Bus the write-back must be latched with EADS to Data Bus be available later. This is required only if AHOLD is not removed if HITM becomes 0. Slow Peripheral Otherwise, the address of the write-back is put onto the address bus by the microprocessor. Enhanced Am486 Microprocessor Normal Write-Back ...
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... BOFF overrides BRDY. Therefore, the partial read is not used reread later. Step 7 One clock cycle later BOFF is deasserted. The write-back access starts one clock cycle later be- cause the BOFF has cleared the bus pipeline. Enhanced Am486 Microprocessor from CPU ...
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... No other access is in progress. Step 2 The processor writes data A to the cache, re- sulting in a write miss. Therefore, the data is put into the write buffers, assuming they are not full. No external access can be started because AHOLD is still 1. Enhanced Am486 Microprocessor from CPU 11 É ...
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... Set the PWT bit in the page table entries. 2) Drive the WB/WT signal Low when accessing these memory locations. Option operating-system level solution not di- rectly implemented by user-level code. Option 2, the hardware solution, is implemented at the system level. Enhanced Am486 Microprocessor B+4 ...
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... BRDY of the copy-back and ADS has been issued, the microprocessor asserts HITM. Keep in mind that the write- back was initiated due to a read miss and not due to a snoop to a modified line. In the second case, no snooping is recog- nized if a modified line is detected. Enhanced Am486 Microprocessor ...
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... Cache Invalidation through Software The Enhanced Am486 microprocessor family uses the same instructions as the Am486DX and Am486 micro- processor families to invalidate the on-chip cache. The two invalidation instructions, INVD and WBINVD, while similar, are slightly different for use in the write-back environment ...
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... CPU 34 PRELIMINARY for cache line write-backs and copy-backs. Standard write operations are still supported because they are on the Am486DX family of microprocessors. Burst writes are always four 32-bit words and start at the beginning First Flush cache line address of 0 for the starting access. The ...
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... The burst write access is finished when BLAST is 0 and BRDY is 0. When the RDY signal is returned instead of the BRDY signal, the Enhanced Am486 microprocessor halts the burst cycle and proceeds with the standard non-burst cycle. 4.10.1 Locked Accesses Locked accesses of an Enhanced Am486 microproces- sor occur for Read-Modify-Write Operations and Inter- rupt Acknowledge Cycles ...
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... The processor drives a special Stop Grant bus cycle to the bus after recognizing the STPCLK interrupt. This bus cycle is the same as the HALT cycle used by a standard Am486 microprocessor, with the exception that the Stop Grant bus cycle drives the value 0000 0010h on the address pins. ...
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... CPU entered the Stop Grant State. For min- imum CPU power consumption, all other input pins should be driven to their inactive level while the CPU is in the Stop Grant state. Enhanced Am486 Microprocessor AMD Stop Grant Bus cycle 37 ...
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... Stop Grant state. However, if one of the interrupt signals (SMI, NMI, or INTR) is driven active while the CPU is in the Stop Grant state, and held active for at least one CLK after STPCLK is deasserted, the corresponding interrupt Enhanced Am486 Microprocessor ...
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... The Enhanced Am486 CPU product family requires INTR to be held active until the CPU issues an inter- rupt acknowledge cycle to guarantee recognition. This condi- tion also applies to the existing Am486 CPUs. In the Stop Grant State, the system can stop or change the CLK input ...
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... The SMI handler then executes the RSM instruction which restores the CPU’s context from SMRAM, deas- serts the SMIACT signal, and then returns control to the previously interrupted program execution. State Save SMI Handler RSM Figure 22. Basic SMI Interrupt Service Enhanced Am486 Microprocessor Instr Instr #4 #5 State Restore ...
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... SMI handler routine for the CPU (from the completion of the interrupted instruction) is given by: Latency to start of SMl handler = 161 clocks and the minimum time required to return to the interrupt- ed application (following the final SMM instruction be- fore RSM) is given by: Latency to continue application = 258 clocks SMI Sampled Enhanced Am486 Microprocessor AMD 41 ...
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... This enables initialization of the SMRAM space (i.e., loading SMI handler) before executing the SMI handler during SMM (see Figure 26). CPU accesses to system address space used for loading SMRAM Figure 26. Redirecting System Memory Enhanced Am486 Microprocessor SMM State ...
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... In this case, the suspend SMI handler should read these registers directly to save them and restore them during the power up resume. Anytime the SMI handler changes these registers in the CPU, it must also save and restore them. Enhanced Am486 Microprocessor AMD 43 ...
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... SMM is latched, and serviced when the processor exits SMM with the RSM instruction. Only one SMI signal is latched by the CPU while SMM. When the CPU invokes SMM, the CPU core registers are initialized as indicated in Table 11. Enhanced Am486 Microprocessor ...
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... In SMM, the CPU can access or jump anywhere within the 4-Gbyte logical address space. The CPU can also indirectly access or perform a near jump anywhere with- in the 4-Gbyte logical address space. Enhanced Am486 Microprocessor AMD 1 Base Attributes ...
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... Note: Changing the state of the reserved bits may result in unpredictable processor behavior SMM Base I/O Trap Relocation Extension 1 1 Default State at SMM State 1 1 Enhanced Am486 Microprocessor 15–0 SMM Revision Level 0000h State at Notes Entry SMM Exit Change in State Change in State 1 ...
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... I/O location was performing either a read ( write (0) operation as indicated by the R/W bit SMI occurs and it does not trap an I/O instruction, the contents of the I/O address and R/W bit are unpre- dictable and should not be used. Enhanced Am486 Microprocessor AMD 0 Register offset 7F00h I/O instruction restart slot 15– ...
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... AMD 7.7.6 SMM Base Relocation The Enhanced Am486 CPU family provides a new con- trol register, SMBASE. The SMRAM address space can be modified by changing the SMBASE register before exiting an SMI handler routine. SMBASE can be changed to any 32K-aligned value. (Values that are not 32K-aligned cause the CPU to enter the Shutdown state when executing the RSM instruction ...
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... Mbyte, and is provided to ensure compatibility with those programs that relied on the physical address wrap around functionality of the original IBM PC. The A20M pin on Enhanced Am486 CPUs provides this function. When A20M is active, all external bus cycles drive A20 Low, and all internal cache accesses are per- formed with A20 Low ...
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... Figure 35. SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with Caching 50 PRELIMINARY SMI Handler Caching Enabled During SMM SMI Handler Enabled During SMM SMI Handler Disabled During SMM Enhanced Am486 Microprocessor Normal Cycle State Resume RSM Normal Cycle State Resume RSM ...
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... Figure 38. SMM Timing in Systems Using Overlaid Memory Spaces and Configured in Write-Back Mode PRELIMINARY SMI Handler Enabled During SMM SMI Handler Disabled During SMM State SMI Handler Save RSM Enhanced Am486 Microprocessor AMD Instruction x+1 Normal State Cycle Resume RSM Cache contents invalidated ...
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... An interrupt or exception cannot transfer control to a segment offset of more than 16 bits exceptions or interrupts are allowed to occur, only the Low order 16 bits of the return address are pushed Enhanced Am486 Microprocessor ...
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... PRELIMINARY 8 TEST REGISTERS 4 AND 5 MODIFICATIONS The Cache Test Registers for the Enhanced Am486 mi- croprocessor are the same test registers (TR3, TR4, and TR5) provided in earlier Am486DX and DX2 micro- processors. TR3 is the cache test data register. TR4, the cache test status register, and TR5, the cache test control register, operate together with TR3 ...
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... Entry selects between one of the four entries in the set addressed by the Set Select during a cache read or write. During cache fill buffer writes or cache read buffer reads, the value in the Entry field selects one of the four doublewords in a cache line. Enhanced Am486 Microprocessor ...
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... TR5. All of the LRU bits, Valid bits, and Set State bits are cleared. 9 Enhanced Am486 CPU Functional Differences Several important differences exist between the En- hanced Am486 microprocessor and the Am486DX mi- croprocessor: n The ID register contains a different version signa- ture. n The EADS function performs cache line write-backs of modified lines to memory in write-back mode ...
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... AMD 10 ENHANCED Am486 CPU IDENTIFICATION The Enhanced Am486 microprocessor supports two standard methods for identifying the CPU in a system. The reported values are dynamically assigned based on the CPU type (DX2 or DX4) and the status of the WB/WT pin input (Low = write-through; High = write- back) at RESET ...
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... V input indicate the presence of CC5 5-V I/O devices on the system motherboard. For socket compatibility, this pin is INC, allowing the Enhanced Am486 CPU to operate in 3-V sockets in systems that use 5-V I/O. PRELIMINARY 11.1.2 Power Decoupling Recommendations Liberal decoupling capacitance should be placed near the microprocessor. The microprocessor, driving its 32- ...
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... Enhanced Am486 Microprocessor Notes Note 1 Note 2 Typical supply current: 528 MHz, 600 MHz, 640 MHz, 800 mA @ 100 MHz, and 960 mA @ 120 MHz Inputs at rails, outputs unloaded. Typical supply current for Stop Grant or ...
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... CLK signal. AC specifications measurement is defined by Figure 36. All timings are referenced to 1.5 V unless otherwise specified. Enhanced Am486 microprocessor Switching Characteristics for 33 MHz bus (66 MHz or 100 MHz operating frequency 3.3 V ±0 0° 85°C; C ...
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... I/O Buffer model must be used to determine delays due to loading (trace and L Enhanced Am486 Microprocessor Unit Figure Notes MHz Note Adjacent Clocks Notes 3 and Note Note Note ...
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... I/O Buffer model must be used to determine delays due to loading (trace and L Enhanced Am486 Microprocessor AMD Unit Figure Notes MHz Note Adjacent Clocks Notes 3 and Note Note Note 3 ns ...
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... AMD Enhanced Am486 Microprocessor AC Characteristics for Boundary Scan Test Signals at 25 MHz V = 3.3 V ±0 0°C to +85° CASE Symbol Parameter t TCK Frequency 24 t TCK Period 25 t TCK High Time TCK Low Time at 0 TCK Rise Time (0.8 V–2 V) ...
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... May change from May change from Don’t care; any change permitted Does not apply Figure 39. CLK Waveforms Figure 40. Output Valid Delay Timing Enhanced Am486 Microprocessor Outputs Will be steady Will change from Will change from Changing; state unknown ...
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... AMD 64 PRELIMINARY Figure 41. Maximum Float Delay Timing Figure 42. PCHK Valid Delay Timing Enhanced Am486 Microprocessor ...
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... PRELIMINARY Figure 43. Input Setup and Hold Timing Figure 44. RDY and BRDY Input Setup and Hold Timing Enhanced Am486 Microprocessor AMD 65 ...
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... AMD 66 PRELIMINARY Figure 45. TCK Waveforms Figure 46. Test Signal Timing Diagram Enhanced Am486 Microprocessor ...
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... CASE (Clock). Note that T heat sink to the package. P (the maximum power con- sumption) is calculated by using the maximum I 3 tabulated in the DC Characteristics . and for the Am486 CPU in 168-Pin PGA Package JC JA vs. Airflow-ft/min. (m/sec) JA 200 400 0 (0) (1 ...
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... AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A Enhanced Am486 Microprocessor Base Plane Seating Plane 0.017 0.020 0.090 0.110 0.105 0.125 0.140 0.180 0.025 0.045 0.110 0.140 Side View ...
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... All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only. AMD, Am386, and Am486 are registered trademarks of Advanced Micro Devices, Inc. FusionPC is a service mark of Advanced Micro Devices, Inc. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corp. ...