82820 Intel Corporation, 82820 Datasheet
82820
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82820 Summary of contents
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... R ® Intel 820 Chipset Family: 82820 Memory Controller Hub (MCH) Datasheet July 2000 Order Number: 290630-002 ...
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... The Intel 82820 Memory Controller Hub (MCH) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... R Contents 1. Overview.....................................................................................................................................13 1.1. Related Documents .......................................................................................................13 ® 1.2. The Intel 1.3. Intel 82820 MCH Overview ..........................................................................................16 2. Signal Description.......................................................................................................................19 2.1. Host Interface Signals ....................................................................................................20 2.2. Direct RDRAM Interface Signals....................................................................................22 2.3. The Hub Interface Signals .............................................................................................22 2.4. AGP Interface Signals....................................................................................................23 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.5. Clock and Reset Signals ................................................................................................28 2.6. Voltage References, Power, Ground, and Test Signals ................................................29 2.7. Strap Signals..................................................................................................................29 2 ...
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... Intel 82820 MCH 3.4.23. 3.4.24. 3.4.25. 3.4.25. 3.4.26. 0) 3.4.27. 3.4.28. 3.4.29. 3.4.30. 3.4.31. 3.4.32. 3.4.33. 3.4.34. 3.4.35. 3.4.36. 3.4.37. 3.4.38. 3.4.39. 3.4.40. 3.4.41. 3.4.42. 3.4.43. 3.4.44. 3.5. AGP Bridge Registers (Device 1) .................................................................................. 77 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 3.5.7. 3.5.8. 3.5.9. 3.5.10. 3.5.11. 3.5.12. 3.5.13. 3.5.14. 3.5.15. 3.5.16. 3.5.17. 3.5.18. 3.5.19. 3.5.20. 3.5.21. 3.5.22. 4 DRD—RDRAM Device Register Data Register (Device 0) ......................... 56 RICM—RDRAM Initialization Control Management Register (Device 0) .... 57 59 SMRAM—System Management RAM Control Register (Device 0) ........... 59 ESMRAMC—Extended System Management RAM Control Register (Device 60 ACAPID ...
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... RDRAM Power Management ........................................................128 Data Integrity .................................................................................129 RDRAM Array Power Management ..............................................129 5.3.1.8.1. RDRAM On-die Internal Thermal Sensor Mechanism (Method 1) ...................................................................130 5.3.1.8.2. RDRAM Reads and Writes Counters/Timers Mechanism (Method 2) ...................................................................130 Processor Power State Control..................................................................132 Sleep State Control ....................................................................................132 ® Intel 82820 MCH 5 ...
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... Intel 82820 MCH 5.6. MCH System Reset and Power Sequencing ............................................................... 134 5.6.1. 5.6.2. 6. Pinout and Package Information .............................................................................................. 137 6.1. Pinout Information ....................................................................................................... 137 6.2. Package Specifications ............................................................................................... 143 6.3. MCH RSL Package Dimensions.................................................................................. 145 7. Testability ................................................................................................................................. 147 6 MCH Reset ................................................................................................ 135 MCH Power Sequence Recommendation................................................. 135 R Datasheet ...
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... Figure 5. MCH/ Direct RDRAM Diagram ................................................................................117 Figure 6. Sideband CMOS Signal Configuration ....................................................................120 Figure 7. RDRAM Throttle Time (With Counters/Timers Mechanism) ...................................131 Figure 8. Intel 82820 MCH Clocking Diagram ......................................................................133 Figure 9. Intel 82820 MCH Reset Overview .........................................................................134 Figure 10. MCH Power-Up Voltage Sequencing ....................................................................135 Figure 11. MCH Ballout (Top View— ...
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... Intel 82820 MCH Tables Table 1. Unsupported Host Bus Signals .................................................................................. 21 Table 2. MCH Strapping Options ............................................................................................. 29 Table 3. Signal States During Reset ........................................................................................ 30 Table 4: MCH PCI Configuration Space (Device 0) ................................................................. 36 Table 5. Attribute Bit Assignment............................................................................................. 50 Table 6. PAM Registers and Associated Memory Segments .................................................. 51 Table 7. MCH Configuration Space (Device 1) ........................................................................ 77 Table 8 ...
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... Revision History Rev. • Initial Release -001 • Added Intel -002 • Removed SDRAM support • Minor edits throughout for clarity. Datasheet Description ® 820E chipset. This change only affected the Overview chapter. ® Intel 82820 MCH Date September 1999 July 2000 9 ...
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... Intel 82820 MCH 10 This page is intentionally left blank. R Datasheet ...
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... AGP, and memory buses supported via dedicated arbitration and data buffering logic ® The Intel 82820 MCH may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Datasheet ! Accelerated Graphics Port (AGP) Interface ...
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... Intel 82820 MCH Simplified Block Diagram HA[31:3]# HD[63:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# CPURST# DQA[8:0] DQB[8:0] RQ[7:5] or ROW[2:0] RQ[4:0] or COL[4:0] CTM, CTM# CFM, CFM# CMD SCK SIO HL[10:0] HL_STB, HL_STB# 12 Host Bus AGP Interface Interface Direct RDRAM Interface Clocks ...
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... This datasheet provides an overview of the 820 chipset family (see Section 1.2). The remainder of the document describes the Intel ® The Intel 82820 MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 1.1. Related Documents • ...
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... Intel 82820 MCH ® 1.2. The Intel 820 Chipset System Figure 1 show a typical system block diagram based on the Intel chipset uses a hub architecture with the MCH as the host bridge hub and the I/O Controller Hub as the I/O hub. The MCH supports processor bus frequencies of 100/133 MHz. The I/O Controller Hub is highly integrated providing many of the functions needed in today’ ...
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... FWH Flash BIOS ® Intel Processor ® Intel 820 Chipset Family Main Memory (Direct RDRAM) Hub Interface PCI Bus (ICH and ICH2) ISA Bridge and (optional) PCI Agent GPIO (ICH and ICH2) 82820 MCH PCI Slots ISA Slots sys_blk 15 ...
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... Intel 82820 MCH Overview The Intel 82820 Memory Controller Hub (MCH) provides the host interface, DRAM interface, I/O interface, and AGP interface in an Intel ® ® the Intel Pentium configurations. The MCH supports a single channel of Direct Rambus memory technology and the AGP interface is fully compliant with the AGP 2.0 specification. Communication to the I/O Controller Hub is made through a private interface (called “ ...
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... Bus frequency, 266 MHz / 356 MHz at 133 MHz Processor System Bus frequency, and 400 MHz at 100 MHz / 133 MHz Processor System Bus frequency.) The AGP interface runs at a constant 66 MHz. The hub interface runs at the same base frequency as the AGP interface. Datasheet Increments Maximum 8 MB 256 512 ® Intel 82820 MCH 17 ...
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... Intel 82820 MCH 18 This page is intentionally left blank. R Datasheet ...
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... Rambus Signaling Level interface signal. Note that RSL channel pins are logically inverted (like AGTL lines). In most cases, a logical value of 0 has a high pin voltage, and a logical value of 1 has a low pin voltage. Refer to the Rambus Specification for complete details. Datasheet ® Intel 82820 MCH 19 ...
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... Intel 82820 MCH 2.1. Host Interface Signals Name Type CPURST# AGTL+ HA[31:3]# AGTL+ HD[63:0]# AGTL+ ADS# AGTL+ BNR# AGTL+ BPRI# AGTL+ DBSY# AGTL+ DEFER# AGTL+ DRDY# AGTL+ HIT# AGTL+ HITM# AGTL+ HLOCK# AGTL+ HREQ[4:0]# AGTL+ HTRDY# AGTL CPU Reset: The CPURST# pin is an output from the MCH. The MCH asserts CPURST# while RSTIN# (PCIRST# from the I/O Controller Hub) is asserted and for approximately 1 ms after RSTIN# is deasserted ...
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... UP processor strapped, DP processors driven from the I/O Controller Hub GPIO through external driver. Bus Error Unrecoverable error without a bus protocol violation Request Parity Parity protection on ADS# and REQ[4:0]# Response Parity Signal Parity protection on RS[2:0]# ® Intel 82820 MCH Description 820/820E chipset. Function that MCH Does Not Support 21 ...
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... Intel 82820 MCH 2.2. Direct RDRAM Interface Signals Name Type DQA[8:0] I/O RSL DQB[8:0] I/O RSL RQ[7: ROW[2:0] RSL RQ[4: COL[4:0] RSL CTM I RSL CTM# I RSL CFM O RSL CFM# O RSL CMD O CMOS SCK O CMOS SIO I/O CMOS 2.3. The Hub Interface Signals Name Type HL[10:0] I/O CMOS ...
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... AGP master (graphics component) to place addresses into the AGP request queue. The SBA bus and AD bus operate independently. That is, transaction can proceed on the SBA bus and the AD bus simultaneously. FRAME# Operation: These signals are not used during AGP FRAME# operation. The SBA[7:0] signals have weak integrated pull-up resistors. ® Intel 82820 MCH 23 ...
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... Intel 82820 MCH 2.4.2. AGP Flow Control Signals Name Type RBF# I AGP WBF# I AGP 2.4.3. AGP Status Signals Name Type ST[2:0] O AGP 24 Description Read Buffer Full: PIPE# and SBA Operation: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted, the MCH is not allowed to initiate the return low priority read data. Thus, the MCH can finish returning the data for the request currently being serviced ...
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... Operation: During 2X operation, this signal is not used. 4X Operation: During 4X operation, this is one-half of a differential strobe pair that provides timing information for the SBA bus signals. The agent that is driving the SBA bus will drive this signal. ® Intel 82820 MCH Description 25 ...
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... Intel 82820 MCH 2.4.5. AGP FRAME# Signals For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similar to their semantics in the PCI 2.1 specification (the AGP interface is NOT PCI 2.1 – 66 MHz compliant). The exact role of all AGP FRAME# signals are defined below. ...
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... PAR is driven by the MCH when it acts as a FRAME# based AGP target during each data phase of a FRAME# based AGP memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#. SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation. ® Intel 82820 MCH 1,2,3 Description 27 ...
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... Intel 82820 MCH 2.5. Clock and Reset Signals Name Type CPUCLK I CMOS CLK66 I CMOS RCLKOUT O CMOS HCLKOUT O CMOS RSTIN# I CMOS 28 Description Host Clock In: CPUCLK receives a buffered host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the Host clock domain. ...
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... Direct Rambus Reference: Reference voltage input for the Direct Rambus RSL interface. AGP Reference: Reference voltage input for the AGP interface. Hub interface Reference: Reference voltage input for the hub interface. AGP I/O Buffer Supply Voltage. 1.8V VCC: Provides 1.8V to the MCH core, as well as 1.8V I/O buffers. Ground. Definition ® Intel Description 82820 MCH 29 ...
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... Intel 82820 MCH 2.8. Pin States During Reset Table 3 indicate the MCH signal pin states during reset assertion. Z Tristate Outputs ISO Isolate Inputs in Inactive State S Strap sampled on RSTIN# rising edge H Driven High L Driven Low D Drive Outputs to Functional Logic Level I Input Active ...
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... That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. Datasheet ® Intel 82820 MCH 31 ...
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... Intel 82820 MCH Symbol Description Reserved In addition to reserved bits within a register, the MCH contains address locations in the Registers configuration space of the Host-Hub Interface Bridge/DRAM Controller and Host-AGP Bridge entities that are marked either "Reserved. When a “Reserved” register location is read, a random value can be returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Registers that are marked as “ ...
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... MCH will generate a configuration cycle over the hub interface. The I/O Controller Hub compares the non-zero Bus Number with the SBUSN and SUBUSN registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI (PCI0 downstream PCI bus. Datasheet ® Intel 82820 MCH 33 ...
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... Intel 82820 MCH AGP Bus Configuration Mechanism From the chipset configuration perspective, AGP is another PCI bus interface residing on a Secondary Bus side of the “virtual” PCI-PCI bridge referred to as the MCH Host-AGP bridge. On the Primary bus side, the “virtual” PCI-PCI bridge is attached to PCI Bus #0. Therefore, the PBUSN register is hardwired to 0. The “ ...
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... CONF_DATA is determined by the contents of the CONF_ADDR register. Bit 31:0 Configuration Data Window (CDW). If bit 31 of CONF_ADDR is 1 any I/O access that to the CONF_DATA register will be mapped to configuration space using the contents of CONF_ADDR. Datasheet Descriptions 0CFCh 00000000h Read/Write 32 bits Descriptions ® Intel 82820 MCH 35 ...
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... Intel 82820 MCH 3.4. Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) Table 4 shows the MCH configuration space for Device 0. An “s” in the Default Value field means that the power-up default value for that bit is determined by a strap. Table 4: MCH PCI Configuration Space (Device 0) Addr ...
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... Reserved Scratchpad Data (not reset) Reserved AGP Buffer Control B Reserved RDRAM Temperature Calibration Enable Reserved AGP Append Disable Reserved ® Intel 82820 MCH Default Value Access 0000h R/W 00h 000000h R/W 00h 02h R/W/L, RO 38h R/W/L 00h ...
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... Intel 82820 MCH 3.4.1. VID—Vendor Identification Register (Device 0) Address Offset: Default: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. ...
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... Memory Access Enable (MAE). (Not Implemented). Hardwired to 1. The MCH always allows access to main memory. Writes to this bit position have no affect. 0 I/O Access Enable (IOAE). (Not Implemented). Hardwired Writes to this bit position have no affect. Datasheet 04–05h 0006h Read/Write 16 bits Descriptions ® Intel 82820 MCH 39 ...
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... Intel 82820 MCH 3.4.4. PCISTS—PCI Status Register (Device 0) Address Offset: Default: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0 on the hub interface. Bit 14 is read/write clear. All other bits are Read Only. Since MCH Device 0 is the Host-to- Hub interface bridge, many of the bits are not implemented ...
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... Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH. 06h = Bridge device. Datasheet 08h 03h Read Only 8 bits Description Value 03h 04h 0Ah 00h Read Only 8 bits Description 0Bh 06h Read Only 8 bits Description ® Intel 82820 MCH 41 ...
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... Intel 82820 MCH 3.4.8. MLT—Master Latency Timer Register (Device 0) Address Offset: Default: Access: Size: The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this register is not implemented. Bit 7:0 These bits are hardwired to 0. Writes have no effect. 3.4.9. HDR—Header Type Register (Device 0) ...
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... Memory Space Indicator—RO. Hardwired identify aperture range as a memory range. Datasheet Description Aperture Size r/w r/w r/w r r/w r/w r r 128 256 MB ® Intel 82820 MCH 43 ...
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... Intel 82820 MCH 3.4.11. SVID—Subsystem Vendor ID Register (Device 0) Offset: Default: Access: Size: This value is used to identify the vendor of the subsystem. Bit 15:0 Subsystem Vendor ID—R/WO. This field should be programmed during boot-up. After this field is written once, it becomes read only. 3.4.12. SID—Subsystem ID Register (Device 0) ...
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... Reserved. 2:1 Device DRAM Technology (DDT). This field defines the DRAM technology of each device in the group 64Mbit/72Mbit 01 = 128Mbit/144Mbit 10 = 256Mbit/288Mbit 11 = Reserved 0 Reserved. Datasheet 40–47h (GAR0–GAR7) 80h Read/Write/Lock 8 bits/register Description ® Intel 82820 MCH 45 ...
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... Intel 82820 MCH 3.4.15. RDTR—RDRAM Timing Register (Device 0) Address Offset: Default: Access: Size: This 32-bit register defines the timing parameters for all devices in all channels. The BIOS programs this register with the “least common denominator” values after reading configuration registers of each device in each channel ...
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... Infinite (pages are not closed for idle conditions) 001 = 0 (Aggressive page closing. A page is closed if no pending request to that page in the pipeline.) 010 = 2 011 = 4 100 = 8 101 = 16 110 = 32 111 = 64 Datasheet 51h 00h Read/Write 8 bits Description 52h 00h Read/Write 8 bits Description ® Intel 82820 MCH 47 ...
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... Intel 82820 MCH 3.4.18. RPMR—RDRAM Power Management Register (Device 0) Address Offset: Default: Access: Size: Bit 7:6 Device Napdown Timer (DNT). This field specifies the number of host clocks the RDRAM channel be at idle before the LRU (Least Recent Used) device in Pool A is pushed out to Pool B. ...
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... Each PAM Register controls two regions, typically 16 KBs. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and are defined in the following table. Datasheet 58h 00h Read/Write 8 bits Description 59–5Fh (PAM0–PAM6) 00h Read/Write 4 bits/register ® Intel 82820 MCH 49 ...
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... Intel 82820 MCH Table 5. Attribute Bit Assignment Bits [7, 3] Bits [6, 2] Reserved Reserved example, consider a BIOS that is implemented on the expansion bus. During the initialization process, BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only ...
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... 0DC000h–0DFFFFh 0E0000h–0E3FFFh 0E4000h–0E7FFFh 0E8000h–0EBFFFh 0EC000h–0EFFFFh ® Intel 82820 MCH Offset 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h Read Enable (R/W 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved pam Comments BIOS Area ...
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... Intel 82820 MCH DOS Application Area (00000h–9FFFh) The DOS area is 640 KB in size and it is further divided into two parts. The 512 KB area 7FFFFh is always mapped to the main memory controlled by the MCH, while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCI0 or to main DRAM ...
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... GBA7 = Total memory in group0 + group1 + group2 + … + group7 (in 8 MBs) Datasheet 60–6Fh (GBA0–GBA7) GBA0 (60–61h) = 0001h GBA4 (60–61h) = 0801h GBA1 (62–63h) = 0201h GBA5 (60–61h) = 0A01h GBA2 (64–65h) = 0401h GBA6 (60–61h) = 0C01h GBA3 (66–67h) = 0601h GBA7 (6E–6Fh) = 0E01h Read/Write/Lock 16 bits/register ® Intel 82820 MCH 53 ...
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... Intel 82820 MCH Bit 15:12 Reserved. 11:9 Group ID Field—RO. This field indicates the GBA group (0–7) that a GBA register belongs to. The fields are hardwired in ascending order. The RDRAM Group ID assignments are as follows: 000 = GBA0 (60–61h) 001 = GBA1 (62–63h) 010 = GBA2 (64–65h) 011 = GBA3 (66– ...
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... If the number of OctWords read/written to RDRAM during this window reaches Throttle DRAM Maximum, then read/write from/to DRAM are blocked for the remainder of the window. Datasheet 80–87h 0000_0000_0000_0000h Read/Write/Lock 64 bits Description 15 to arrive at the number of ® Intel 82820 MCH 55 ...
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... Intel 82820 MCH Bits 12:3 Throttle DRAM Maximum (TDM). The Throttle DRAM Maximum defines the maximum number of OctWords between 0–1023 which are permitted to be written to and read from DRAM within one Throttle Monitoring Window while the RDRAM throttling mechanism is in effect. RDRAM throttling is invoked with either the START bit or the Counter mechanism ...
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... ID for Powerdown Entry, Powerdown Exit, Nap Entry, Nap Exit, Current Calibrate and Current Calibrate and Sample IOP commands. • the bank address for Refresh and Precharge IOP commands Datasheet 94–96h 000000h Read/Write 24 bits Description ® Intel 82820 MCH 57 ...
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... Intel 82820 MCH Bit 3:0 Initialization Opcode (IOP). This field, along with bit 18, specifies the initialization operation to be done on RDRAM device or MCH RAC. Bits[18, 3:0] 0, 0000 0, 0001 0, 0010 0, 0011 0, 0100 0, 0101 to 0, 1010 0, 1011 0, 1100 to 0, 1111 1, 0000 1, 0001 1, 0010 1, 0011 1, 0100 ...
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... SMM space. "SMM DRAM" is not remapped simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to the hub interface. C_BASE_SEG is hardwired to 010 to indicate that the MCH supports the SMM space at A0000h–BFFFFh. Datasheet 9Dh 02h Read/Write/Lock, Read Only 8 bits Description ® Intel 82820 MCH 59 ...
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... Intel 82820 MCH 3.4.26. ESMRAMC—Extended System Management RAM Control Register (Device 0) Address Offset: Default: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. ...
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... End of the capability linked list 7:0 AGP Capability ID. This field identifies the linked list item as containing AGP registers. This field has the value 0000_0010b as assigned by the PCI SIG. Datasheet A0–A3h 00200002h Read Only 32 bits Description compliant device. ® Intel 82820 MCH 61 ...
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... Intel 82820 MCH 3.4.28. AGPSTAT—AGP Status Register (Device 0) Address Offset: Default: Access: Size: This register reports AGP device capability/status. Bit 31:24 RQ. Hardwired to 1Fh. 1Fh = Maximum of 32 outstanding AGP command requests can be handled by the MCH. 23:10 Reserved 9 SBA. Hardwired to 1. This bit indicates that the MCH supports side band addressing. ...
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... AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space.) Note: This field applies to AD and SBA buses. It also applies to Fast Writes if they are enabled. 001 = 1x 010 = 2x 100 = 4x All other bit combinations are illegal Datasheet A8–ABh 00000000h Read/Write 32 bits Description ® Intel 82820 MCH 63 ...
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... Intel 82820 MCH AGPCTRL AGP Control Register (Device 0) 3.4.30. Address Offset: Default: Access: Size: This register provides for additional control of the AGP interface. Bit 31:2 Reserved 1 Fast Write Capability Enable (FWCE). To use Fast Write Protocol, both this bit and FWPE Enable bit (bit 4 of AGPCMD) must be set to 1 ...
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... APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write programmable. Datasheet B4h 00h Read/Write 8 bits Description Aperture Size 128 256 MB ® Intel 82820 MCH 65 ...
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... Intel 82820 MCH 3.4.32. ATTBASE—Aperture Translation Table Base Register (Device 0) Address Offset: Default: Access: Size: This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DRAM. This value is used by the MCH Graphics Aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical DRAM address ...
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... Host Frequency—RO. This bit is used to determine the host frequency of the Processor System Bus set by an external strapping option at reset and is Read Only 100 MHz 1 = 133 MHz Datasheet BDh 00h Read/Write 8 bits Description BE–BFh 00s0_0000_ 0000_0s00b Read/Write, Read Only 16 bits Description ® Intel 82820 MCH 67 ...
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... Intel 82820 MCH Bit 12:11 Rambus Frequency—R/W. These bits are written by the BIOS after polling the Rambus DRAMs and finding the least common denominator speed. The Host-Bus Frequency (Bit 13 of this register) must also be used to determine the exact RDRAM frequency. ...
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... A multiple bit error overwrites a single bit error. This register is loaded, locked, and unlocked along with the EAP field. Datasheet Description C4–C7h XXXXXXXXh (X=Undefined) Read Only 32 Bits Description ® Intel 82820 MCH 69 ...
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... Intel 82820 MCH 3.4.37. ERRSTS—Error Status Register (Device 0) Address Offset: Default: Access: Size: This register is used to report various error conditions via the hub interface cycles. An SERR, SMI, or SCI error message may be generated (on a zero to one transition of any of these flags) via the hub interface when enabled in the respective PCICMD/ERRCMD, SMICMD, or SCICMD registers ...
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... EAP and ES fields with the multiple bit error address and syndrome and the MEF bit will also be set Software must write clear this bit and unlock the error logging mechanism. Datasheet Intel Description ® 82820 MCH 71 ...
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... Intel 82820 MCH ERRCMD Error Command Register (Device 0) 3.4.38. Address Offset: Default: Access: Size: This register enables various errors to generate a SERR message via the hub interface. Since the MCH does not have an SERR# signal, SERR messages are passed from the MCH to the I/O Controller Hub over the hub interface ...
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... SERR on Single-bit ECC Error Enable. SERR error message via the hub interface will be generated by the MCH when it detects a Single-bit ECC error. For systems that do not support ECC this field must be set Disable reporting of this condition. Datasheet Intel Description ® 82820 MCH 73 ...
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... Intel 82820 MCH SMICMD SMI Command Register (Device 0) 3.4.39. Address Offset: Default: Access: Size: This register enables various errors to generate a SMI hub interface special cycle. When an error flag is set in the ERRSTS register it can generate a SERR, SMI, or SCI hub interface special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. Note: An error can generate one and only one hub interface error special cycle software’ ...
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... Size: This register is not reset with RSTIN#. It defaults to an indeterminate value. Bit 15:0 Scratchpad [15:0]. These bits are simply R/W storage bits that have no effect on the MCH functionality. Datasheet CDh 00h Read/Write 8 bits Description DE–DFh XXXXh (X=Undefined) Read/Write 16 bits Description ® Intel 82820 MCH 75 ...
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... Intel 82820 MCH 3.4.42. AGPBCTRL—AGP Buffer Control B Register (Device 0) Address Offset: Default: Access: Size: This register provides additional control of the 3.3V AGP buffer strength. Bit 31:16 AGP Buffer Strength Control 1. 15:13 AGP Buffer Strength Control 2. 12:0 Reserved 3.4.43. RTCE—RDRAM Temperature Calibration Enable Register (Device 0) ...
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... Memory Limit Address Register PMBASE Prefetchable Memory Base Address Reg. PMLIMIT Prefetchable Memory Limit Address Reg. Reserved BCTRL Bridge Control Register Reserved ERRCMD1 Error Command Reserved ® Intel 82820 MCH Default Value Access 8086h RO 250Fh RO 0000h RO, R/W 0020h RO, R/WC 03h RO 00h 04h RO ...
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... Intel 82820 MCH 3.5.1. VID1—Vendor Identification Register (Device 1) Address Offset: Default: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. ...
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... Disable. All of Device 1’s memory space is disabled. 0 I/O Access Enable (IOAE1)—R/ Enable. This bit must be set enable the I/O address range defined in the IOBASE, and IOLIMIT registers Disable. All of Device 1’s I/O space is disabled Datasheet 04–05h 0000h Read/Write, Read Only 16 bits Descriptions ® Intel 82820 MCH 79 ...
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... Intel 82820 MCH 3.5.4. PCISTS1—PCI-PCI Status Register (Device 1) Address Offset: Default: Access: Size: PCISTS1 reports the occurrence of error conditions associated with the primary side of the “virtual” PCI- PCI bridge in the MCH. Since this device does not physically reside on PCI0, it reports the optimum operating conditions so that it does not restrict the capability of PCI0 ...
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... Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH Device 1. 06h = Bridge device. Datasheet 08h 03h Read Only 8 bits Description Value 03h 04h 0Ah 04h Read Only 8 bits Description 0Bh 06h Read Only 8 bits Description ® Intel 82820 MCH 81 ...
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... Intel 82820 MCH 3.5.8. MLT1—Master Latency Timer Register (Device 1) Address Offset: Default: Access: Size: This functionality is not applicable described here since these bits should be implemented as a read/write to prevent standard PCI-PCI bridge configuration software from getting “confused” . Bit 7:3 Not applicable, but support read/write operations. ...
Page 83
... This register identifies the subordinate bus (if any) that resides at the level below AGP. Bit 7:0 Subordinate Bus Number. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP. (Default = 00h) Datasheet 19h 00h Read /Write 8 bits Descriptions 1Ah 00h Read /Write 8 bits Descriptions ® Intel 82820 MCH 83 ...
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... Intel 82820 MCH 3.5.13. SMLT—Secondary Master Latency Timer Register (Device 1) Address Offset: Default: Access: Size: This register controls the bus tenure of the MCH on AGP. MLT controls the amount of time the MCH as a AGP/PCI bus master, can burst data on the AGP/PCI Bus. The count value bit quantity; ...
Page 85
... FFFh. Thus, the top of the defined I/O address range is at the top aligned address block. Bit 7:4 I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default=0h 3:0 Reserved. Datasheet 1Ch F0h Read/Write 8 bits Description 1Dh 00h Read/Write 8 bits Description ® Intel 82820 MCH 85 ...
Page 86
... Intel 82820 MCH 3.5.16. SSTS—Secondary PCI-PCI Status Register (Device 1) Address Offset: Default: Access: Size: SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., AGP side ) of the “virtual” PCI-PCI bridge embedded within MCH. Bit 15 Detected Parity Error (DPE1) ...
Page 87
... This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP memory access performance. Bit 15:4 Memory Address Limit (MEM_LIMIT). Corresponds to A[31:20] of the memory address. (Default=0s) 3:0 Reserved. Datasheet 20–21h 0000h Read/Write 16 bits Description 22–23h 0000h Read/Write 16 bits Description ® Intel 82820 MCH 87 ...
Page 88
... Intel 82820 MCH 3.5.19. PMBASE—Prefetchable Memory Base Address Register (Device 1) Address Offset: Default: Access: Size: This register controls the host to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE≤address ≤PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address ...
Page 89
... All references to MDA and VGA go to the hub interface. 1 Illegal combination (DO NOT USE) 0 All references to VGA go to AGP. MDA-only references (I/O Address 3BFh and aliases) will go to the hub interface. 1 VGA references go to AGP; MDA references go to the hub link. ® Intel 82820 MCH 89 ...
Page 90
... Intel 82820 MCH Bit 2 ISA Enable. Modifies the response by the MCH to an I/O access issued by the host that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers MCH doesl not forward to AGP any I/O transactions addressing the last 768 bytes in each 1 KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers ...
Page 91
... System Address Map The 82820 MCH supports addressable memory space and 64 KB+3 of addressable I/O space. Note the supported DRAM technology has limited the total physical memory size to 1 GB. There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only ...
Page 92
... Intel 82820 MCH Figure 3. Detailed Memory System Address Map Window For Non-Prefetchable PCI accesses to AGP (Base=MBASE Reg. (20h); Dev 1) (Size=MLIMIT Reg. (22h); Dev 1) Window For Prefetchable PCI accesses to AGP (Base=PMBASE Reg. (24h); Dev 1) (Size=PMLIMIT Reg. (26h); Dev 1) AGP Aperture Range (Base=APBASE Reg. (10h) ...
Page 93
... ® Intel 82820 MCH Comments 0 to 640K; DOS Region Video Buffer (physical DRAM configurable as SMM space) Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS ...
Page 94
... Intel 82820 MCH Compatible SMRAM Address Range (A0000h–BFFFFh) When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed to physical DRAM at this address. Non-SMM-mode processor accesses to this range are considered the Video Buffer Area as described above. Originated cycles from AGP or the hub interface to enabled SMM space are not allowed and are considered the Video Buffer Area. Monochrome Adapter (MDA) Range (B0000h– ...
Page 95
... DRAM). The exception is Non-SMM mode Write Back cycles that are directed to the physical SMM space to maintain cache coherency. Originated cycle from AGP or the hub interface to enable SMM space is not allowed. Datasheet ® Intel 82820 MCH 95 ...
Page 96
... Intel 82820 MCH PCI Memory Address Range (Top of Main Memory to 4 GB) The address range from the top of main DRAM (top of physical memory space supported by the Intel 820/820E chipset) is normally mapped to the hub interface. There are two exceptions: • Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT, PMBASE, and PMLIMIT registers are mapped to AGP. • ...
Page 97
... Note: Plug-and-play software configuration model does not allow overlap of different address ranges. Therefore, the AGP Graphics Aperture and AGP Memory Address Range are independent address ranges that may be adjacent but cannot overlap one another. Datasheet ® Intel 82820 MCH 97 ...
Page 98
... Intel 82820 MCH 4.1.5. System Management Mode (SMM) Memory Range The MCH supports the use of main memory as System Management RAM (SMRAM) enabling the use of System Management Mode. The MCH supports two SMRAM options: • Compatible SMRAM (C_SMRAM) • Extended SMRAM (E_SMRAM). ...
Page 99
... G_SMRAME Datasheet High Enable TSEG Enable H_SMRAM_EN TSEG_EN ® Intel Compatible High (H) (C) Range Range Disable Disable Enable Disable Enable Disable Disabled Enable Disabled Enable 82820 MCH TSEG (T) Range Disable Disable Enable Disable Enable 99 ...
Page 100
... Intel 82820 MCH SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to hub interface #1 or AGP ...
Page 101
... The I/O ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh. Note: The MCH Device 1 I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on AGP. Datasheet ® Intel 82820 MCH 101 ...
Page 102
... Intel 82820 MCH 4.3. MCH Decode Rules and Cross-Bridge Address Mapping The address map described above applies globally to accesses arriving on any of the three interfaces (i.e., Host bus, the hub interface, or AGP). 4.3.1. The Hub Interface Decode Rules The MCH accepts accesses from the hub interface to the following address ranges: • ...
Page 103
... Any I/O reference that includes the I/O locations listed above, or their aliases, are forwarded to the hub interface, even if the reference includes I/O locations not listed above. Datasheet 0B0000h–0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode) ® Intel 82820 MCH 103 ...
Page 104
... Intel 82820 MCH VGA Enable: Controls the routing of host-initiated transactions targeting VGA compatible I/O and memory address ranges. When this bit is set , the MCH forwards the following host accesses to AGP: • Memory accesses in the range 0A0000h to 0BFFFFh • I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh ...
Page 105
... R 5. Functional Description This chapter covers the 82820 MCH functional units including, host interface, AGP interface, power management, clocking, and system reset and power sequencing. 5.1. Host Interface The MCH is optimized for the Intel one or two processor configuration for slot 1. The MCH supports Processor System Bus frequencies of 100 MHz and 133 MHz using AGTL+ signaling ...
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... Intel 82820 MCH Transaction Reserved Reserved I/O Read I/O Write Reserved Memory Read and Invalidate Reserved Memory Code Read Memory Data Read Memory Write (no retry) Memory Write (can be retried) NOTES: 1. For Memory cycles, REQa[4:3]# = ASZ#. The MCH only supports ASZ (32 bit address). ...
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... Implicit Writeback This response is given for those transactions where the initial transactions snoop hits on a modified cache line. 1 Normal Data This response is for transactions where data Response accompanies the response phase. Reads receive this response. ® Intel 82820 MCH MCH Support 107 ...
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... Intel 82820 MCH Cache Line Reads A read of a full cache line (as indicated by the LEN[1:0]=10 during request phase) requires 32 bytes of data to be transferred, which translates into four data transfers for a given request. If selected as a target, the MCH determines if the address is directed to DRAM, the hub interface, or AGP and provides the corresponding command and control to complete the transaction ...
Page 109
... Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carry the linear address of the instruction causing the branch and D[31:0]# carry the target linear address. The MCH responds and retires this transaction but does not latch the value on the data lines or provide any additional support for this type of cycle. Datasheet ® Intel 82820 MCH 109 ...
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... Intel 82820 MCH Special Cycles A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. In the first address phase, Aa[35:3]# is undefined and can be driven to any value. In the second address phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. All Host-initiated Special Cycles are routed to the hub interface. Special Cycles are “ ...
Page 111
... The MCH is optimized for uniprocessor system but supports the symmetrical multiprocessor configurations two processors on the Processor System Bus for slot 1. When configured for dual-processor, the 82820 MCH-based platform must integrate I/O APIC functionality and the associated buffer management required with an I/O APIC is handled via the special cycles on the hub interface ...
Page 112
... Intel 82820 MCH 5.2. AGP Interface The MCH supports 3.3V AGP 1x/2x, and 1.5V AGP 1x/2x/4x devices. The AGP signal buffers have two modes of operation; 3.3V drive/receive (buffers are not 5 volt tolerant), and 1.5V drive/receive (buffers are not 3.3 volt tolerant). The MCH supports 2x/4x clocking transfers for read and write data, and sideband addressing ...
Page 113
... MCH 1011 N/A 1100 MCH 1101 N/A 1110 N/A 1111 N/A Signaling Level 1.5v 3.3v Yes Yes Yes Yes Yes No ® Intel 82820 MCH MCH Host Bridge Response as PCIx Target Complete with QW of Random Data No Response No Response - Flag inserted in MCH request queue No Response No Response No Response 113 ...
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... Intel 82820 MCH 5.2.4. 4x AGP Protocol In addition to the 1x and 2x AGP protocol, the MCH supports 4x AGP read and write data transfers and 4x sideband address generation. The 4x operation is compliant with AGP 2.0 specification. The MCH indicates that it supports 4x data transfers through RATE[2] (bit 2) of the AGP Status Register ...
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... Main Memory 1100 The Hub interface 1101 N/A 1110 Main Memory 1110 The Hub interface 1111 Main Memory 1111 The Hub interface ® Intel 82820 MCH 1 MCH Response as A FRAME# Target No Response No Response No Response No Response No Response No Response Read No Response Posts Data No Response ...
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... Intel 82820 MCH As a target of an AGP FRAME# cycle, the MCH only supports the following transactions: • Memory Read, Memory Read Line, and Memory Read Multiple. These commands are supported identically by the MCH. The MCH does not support reads of the hub interface bus from AGP. ...
Page 117
... Figure 4. MCH/ Direct RDRAM Diagram The maximum system memory supported by the MCH depends on the Direct RDRAM device technology. The following table shows the maximum memory supported in various configurations. Datasheet RIMM_0 MCH CFM/CFM#/RSL/CMOS Signals CTM/CTM# Signals ® Intel 82820 MCH RIMM_1 DRCG Term RDRAM_2RIMM 117 ...
Page 118
... Intel 82820 MCH Table 17. Maximum Supported Direct RDRAM Configurations Direct RDRAM Technology 64Mbit 128Mbit 256Mbit The row, column, and bank address bits required for the Direct RDRAM device depends on the number of banks and page size of the device. The following table shows the different combinations supported by the MCH ...
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... Datasheet Direct Rambus Channel Frequency / Processor System Bus Frequency (both in MHz) 266 / 133 300 / 100 356 / 133 Group Name Group#0 Group#1 Group#2 Group#3 Group#4 Group#5 Group#6 Group#7 ® Intel 82820 MCH 400 / 100 400 / 133 X X 119 ...
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... Intel 82820 MCH 5.3.1.1.2. RDRAM CMOS Signals Description and Usage There are 3 CMOS signal pins on the MCH to support Direct RDRAM device configuration, SIO reset, register accesses, and Nap and PowerDown exits. These signals are SCK, CMD and SIO and are used to perform the following operations: • ...
Page 121
... RDRAM generation. Datasheet # of Banks Device (D = dependent) Capacity 16 ( 2x16 ( 2x16 ( 2x16 ( 2x16 ( ® Intel Refresh Page Size Required Interval Refresh Rate 7.8 us 82820 MCH 121 ...
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... Intel 82820 MCH Refreshes for RDRAM Devices in Nap Mode When the devices are in the Nap mode, their DLLs need to be refreshed every maintain the accurate phase information. Nap exit is performed by sending device ID on the DQ lines along with Rambus CMOS control signals. An RDRAM device can remain in Nap mode for a maximum period of time before it must be brought out of Nap mode, into Standby or Active ...
Page 123
... Device address Bank Address Row address Select between ROWA and ROWR, Active Row Opcode for Primary Control Packet Reserved ® Intel Cycle 2 Cycle 3 R[10] R[8] R[5] R[2] R[9] R[7] R[4] R[ R[6] R[3] R[0] Cycle 2 Cycle 3 ROP[10] ROP[8] ROP[5] ROP[9] ROP[7] ROP[ ROP[6] ROP[3] 82820 MCH ROP[2] ROP[1] ROP[0] 123 ...
Page 124
... Intel 82820 MCH Table 26. ROWA and ROWR Packet Field Encodings NOTES Controller drives Controller drives 0 3 ...
Page 125
... Cycle 0 Cycle COP[1] COP[0] COP[2] COP[2] COP[1] COP[ Cycle 0 Cycle 1 MA[7] MA[ MA[6] MA[4] MB[7] MB[4] MB[6] MB[3] MB[5] MB[2] ® Intel 82820 MCH Cycle 2 Cycle 3 REV C[5] REV BC[2] BC[4] BC[1] COP[3] BC[3] BC[0] Command Description No operation NOCOP. Retire write buffer of this device Write Read Cycle 2 Cycle 3 MA[3] MA[1] MA[2] MA[0] MB[1] MB[0] C[4] C[3] C[2] C[1] C[0] 125 ...
Page 126
... Intel 82820 MCH Table 30. COLX Packet ( Column COL4 COL3 COL2 COL1 COL0 NOTES: 1. DX[4:0] Device ID for Extra operation 2. BX[4:0] Bank Address for Extra operation 3. MA[7:0] Byte Mask (low order) 4. MB[7:0] Byte Mask (high order) 5. XOP[4:0] Opcode for Extra Operation 6. REV Reserved Table 31. COLM Packet and COLX Packet Field Encodings ...
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... Device Ready to receive row packet . with fast clock Device ready to receive any control packet Device ready to receive any control packet. Transmitting data on channel Device ready to receive any control packet. Receiving data from channel ® Intel 82820 MCH Refresh RDRAM Scheme Clock State Self Refresh stopped Active Refresh ...
Page 128
... Intel 82820 MCH 5.3.1.5. RDRAM Operating Pools To minimize the operating power the RDRAM devices are grouped into two operating pools called Pool “A” and Pool “B”. Pool “A” and Pool “B” Operation devices can be in Pool “A” time out Pool “A” can be in Active Read/Write or Active state at a time. The devices in Pool “ ...
Page 129
... A multiple bit error will overwrite the EAP register. Subsequent multiple bit errors will not overwrite the EAP register unless the multiple bit error status bit is cleared. Note: When an 82820-based platform is configured for ECC support multi-bit uncorrectable memory error is detected during a memory read by a system device, an SERR, SCI, or SMI will be generated. This typically results in an NMI ...
Page 130
... Intel 82820 MCH 5.3.1.8.1. RDRAM On-die Internal Thermal Sensor Mechanism (Method 1) With the on-die thermal sensors for each RDRAM device and the Current Calibration protocol specified by Direct RDRAM channel, the MCH can trigger the RDRAM throttling based on the settings of the TEMP register in the RDRAM device and the DTC register in the MCH. ...
Page 131
... RDRAM Throttle Threshold 0 (GDT) Throttle Time (TT sample ) 16B (TDM) idle idle 0-1023 0-2047 HCLKs Throttle Monitor Window (TMW) ® Intel 82820 MCH 1020 ms When threshold exceeded, 128M throttling kicks in OctWords (2GB) rdram_pwr_1 (63 x sample 64.3 sec window) idle idle RDRAM_throttle_Time 131 ...
Page 132
... Intel 82820 MCH 5.4. Power Management The platform is compliant with the following specifications: • APM Rev 1.2 • ACPI Rev 1.0 • PCI Power Management Rev 1.0 • PC'97, Rev 1.0 • PC’98, Rev 1.0 5.4.1. Processor Power State Control • C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is deasserted and the processor core is active ...
Page 133
... With 100 MHz host bus clock, DRCG supports 300 or 400 MHz clock speed for the Direct Rambus channel. The clock connections to the various blocks for MCH are shown in the following block diagram. Figure 7. Intel 82820 MCH Clocking Diagram Slot 1 picclk bclk MCH ...
Page 134
... ITP. CPURST# is deasserted synchronous to the host bus clock. CPURST# is deasserted approximately 1msec (65536 66 MHz clocks) after detecting the rising edge of RSTIN#. Figure 8. Intel 82820 MCH Reset Overview PWRGOOD Note: This diagram does not represent all the details for schematics connection. 134 ...
Page 135
... For further details on the voltage regulator design, refer to the appropriate chipset design guide (Intel Design Guide). Figure 9. MCH Power-Up Voltage Sequencing Datasheet ® 820 Chipset Design Guide or Intel V 3 2 1.0 Figure: MCH Power-Up Voltage Sequencing ® Intel 82820 MCH ® 820E Chipset t Time 135 ...
Page 136
... Intel 82820 MCH 136 This page is intentionally left blank. R Datasheet ...
Page 137
... Pinout and Package Information 6.1. Pinout Information This section lists the MCH ballout assignment. The following two figures show the footprint ballout assignments from a top view of the package. The following table lists the ballout assignment in alphabetical order by signal name. Datasheet ® Intel 82820 MCH 137 ...
Page 138
... Intel 82820 MCH Figure 10. MCH Ballout (Top View—Left Side) 1 VSS HCLKOUT A RCLKOUT SCK B RS1# SIO C DBSY# ADS# D HITM# RS2# E DRDY# DEFER# F BPRI# HREQ4# G HREQ0# HA9# H HA3# HA14# J HA13# HA7# K HA11# HA19# L HA23# HA22# M HA27# HA20# N HA26# HA28# P HD1# HD0# ...
Page 139
... HD55# AGPREF G_REQ# SBA7 VSS HD62# WBF# RBF# HD63# HD58# ST0 PIPE# HD56# HD61# ST1 G_GNT ® Intel 82820 MCH VSS HLCOMP VSS HL7 VCC1_8 HL6 HL5 HL4 VCC1_8 HL9 VCC1_8 HL_STB# HL8 HL10 HL_STB VSS HL2 ...
Page 140
... Intel 82820 MCH Table 35. MCH Alphabetical Ball List Name Ball # AD_STB0 J19 AD_STB0# H20 AD_STB1 R18 AD_STB1# R19 ADS# D2 AGPREF U14 BNR# F5 BPRI# G1 CFM A12 CFM# B12 CLK66 W18 CMD B3 CPURST# P4 CTM B11 CTM# A11 DBSY# D1 DEFER# F2 DQA0 A13 DQA1 ...
Page 141
... RQ0 A7 VCC1_8 RQ1 C8 VCC1_8 RQ2 A8 VCC1_8 RQ3 C9 VCC1_8 RQ4 B9 VCC1_8 RQ5 A9 VCC1_8 RQ6 A10 VCC1_8 RQ7 C10 ® Intel 82820 MCH Ball # Name Ball # E5 VCC1_8 G6 C1 VCC1_8 P15 E2 VCC1_8 R6 F20 VCC1_8 R7 Y20 VCC1_8 T14 Y19 VDDQ F15 W20 VDDQ J17 V17 ...
Page 142
... Intel 82820 MCH Name Ball # VSS F16 VSS G3 VSS H19 VSS J3 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 VSS K11 142 Name Ball # Name VSS K12 VSS VSS K19 VSS VSS L3 VSS VSS L5 VSS VSS L9 VSS VSS ...
Page 143
... This section shows the mechanical dimensions for the MCH. The package is a 324 Ball Grid Array (BGA). Figure 12. Package Dimensions (324 BGA) – Top and Side Views Pin A1 corner Pin A1 I.D. 45° Chamfer (4 places Datasheet D D1 Top View A Side View ® Intel 82820 MCH E1 E 30° -C- Seating Plane pkgbga_top&side.vsd 143 ...
Page 144
... Intel 82820 MCH Figure 13. Package Dimensions (324 BGA) – Bottom View Table 36. BGA Package Dimensions (324 BGA) Symbol 26.80 D1 23.80 E 26.90 E1 23. NOTES: 1. All dimensions and tolerances conform to ANSI Y14.5-1982 2. Dimension is measured at maximum solder ball diameter parallel to primary datum (-C-) 3 ...
Page 145
... B5 152.47 ® Intel Signal Ball on Package Dimension* MCH (mils) DQB7 A4 237.71 DQB8 C4 138.29 RQ0 A7 179.49 RQ1 C8 27.12 RQ2 A8 162.21 RQ3 C9 5.80 RQ4 B9 71.70 RQ5 A9 133.88 RQ6 A10 122.20 RQ7 C10 0.00 CFM A12 132.37 CFM# B12 64.63 CTM B11 56.06 CTM# A11 126.34 82820 MCH 145 ...
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... Intel 82820 MCH 146 This page is intentionally left blank. R Datasheet ...
Page 147
... Any unsoldered pin will cause “XOR out” not to toggle. Datasheet Input Input BIDR Output Output ® Intel 82820 MCH XOR Out Input BIDIR xor.vsd 147 ...
Page 148
... Intel 82820 MCH Initialization Sequence Five pins need to be controlled to enable XOR chain and “tri-state all pins” test modes as shown in Figure 14. Figure 14. Initialization Sequence AGPCLK RSTIN# GRCOMP/TEST ST[2:1] Desired Test Mode (internal signal) GRCOMP signal is held high for N number of rising edges of AGPCLK ticks, where: ...
Page 149
... HA19# HA17# HA31# HA25# HA23# HA22# HA27# HA26# HD1# HA21# HA20# HA28# HD0# HD4# HD10# HA30# HA29# HD9# CPURST# HA24# HD20# SBA0 W20 ® Intel 82820 MCH Chain Note Element # ...
Page 150
... Intel 82820 MCH Table 39. XOR Chain #2 Connections NAME BALL Chain Element # HD13 HD15 HD6 HD23 HD2 HD12 HD19 HD14 HD8 HD5 HD25 HD3 HD7 HD17 HD18# ...
Page 151
... G_AD11 G_AD9 Dependency on G_AD14 complement signal in Chain #4 G_AD8 G_AD12 AD_STB0 G_AD7 G_AD6 G_AD5 G_AD3 G_AD1 G_AD2 G_C/BE0# HL_STB Dependency on complement signal in Chain #4 SB_STB# ® Intel 82820 MCH BALL Chain Note Element # N20 33 M18 34 L16 35 M20 36 K16 37 L18 38 L19 39 L20 40 K17 41 K18 ...
Page 152
... Intel 82820 MCH Table 41. XOR Chain #4 Connections NAME BALL Chain Element # SBA4 V20 1 AD_STB1# R19 2 AD_STB0# H20 3 G_AD4 G16 4 G_AD0 F17 5 HL0 F19 6 HL1 F18 7 HL2 E17 8 HL3 E19 9 HL8 D17 10 HL10 D18 11 HL_STB# C20 12 HL9 C18 13 HL4 B20 14 HL5 ...