MB81G83222-010 Fujitsu, MB81G83222-010 Datasheet

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MB81G83222-010

Manufacturer Part Number
MB81G83222-010
Description
CMOS 2 x 128K x 32 SYNCHRONOUS GRAM
Manufacturer
Fujitsu
Datasheet

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FUJITSU SEMICONDUCTOR
MEMORY
CMOS 2
SYNCHRONOUS GRAM
MB81G83222-010/-012/-015
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Voltage of V
Voltage at any pin relative to V
Short Circuit Output Current
Power Dissipation
Storage Temperature
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS (See NOTE)
The Fujitsu MB81G83222 is a CMOS Synchronous Graphic Random Access Memory (SGRAM) containing
8,388,608 memory cells accessible in an 32-bit format. The MB81G83222 features a fully synchronous operation
referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high
performance and simple user interface coexistence. The MB81G83222 SGRAM is designed to reduce the
complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and
may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB81G83222 is ideally suited for Graphics workstations, laser printers, high resolution graphic adapters,
accelerators and other applications where an extremely large memory and bandwidth are required and where a
simple interface is needed.
DATA SHEET
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CC
Parameters
Supply relative to V
SYNCHRONOUS GRAPHIC RANDOM ACCESS MEMORY
CMOS 2 BANKS OF 131,072-WORDS
SS
SS
128K
V
V
Symbol
CC
IN
T
I
, V
, V
P
OUT
STG
D
OUT
CCQ
32
–0.5 to +4.6
–0.5 to +4.6
–55 to +125
32-BIT
Value
1.2
50
DS05-12101-2E
Unit
mA
W
V
V
C
1

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MB81G83222-010 Summary of contents

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... FUJITSU SEMICONDUCTOR DATA SHEET MEMORY CMOS 2 SYNCHRONOUS GRAM MB81G83222-010/-012/-015 CMOS 2 BANKS OF 131,072-WORDS SYNCHRONOUS GRAPHIC RANDOM ACCESS MEMORY DESCRIPTION The Fujitsu MB81G83222 is a CMOS Synchronous Graphic Random Access Memory (SGRAM) containing 8,388,608 memory cells accessible in an 32-bit format. The MB81G83222 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence ...

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... Byte control by DQM to DQM 0 • Burst read/write operation and burst read/single write operation capability PACKAGE Package and Ordering Information – 100-pin plastic QFP , order as MB81G83222- 2 MB81G83222-010 MB81G83222-012 100 MHz max. 84 MHz max min max max min. 280 mA max. ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 PIN ASSIGNMENTS AND DESCRIPTIONS CCQ SSQ CCQ SSQ CCQ SSQ CCQ ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 CLK CLOCK BUFFER CKE CS RAS COMMAND DECODER CAS WE DSF ADDRESS BUFFER REGISTER to & BANK SELECT DQM 0 to DQM 3 I/O DATA BUFFER/ REGISTER Fig MB81G83222 BLOCK DIAGRAM To each block RAS CONTROL CAS SIGNAL LATCH WE MODE REGISTER ROW ADDR ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTION TRUTH TABLE COMMAND TRUTH TABLE Function Notes Symbol Device Deselect 5 No Operation 5 Burst Stop 6 Read 7 Read With Auto-precharge 7 Write 7 Write With Auto-precharge 7 Block Write 7 Block Write with 7 Auto-precharge Bank Active (RAS) 7 & WPB Disable Bank Active (RAS) 8 & WPB Enable ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) DQM TRUTH TABLE Function i-th Byte Write Enable / Output Enable i-th Byte Data Mask / Output Disable Notes:1. i= DQM for DQM CKE TRUTH TABLE Current State Function Clock Suspend Mode Bank Active Entry Any ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Aplicable to single bank) Current CS RAS CAS WE DSF State Idle Bank Active ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Read Write ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Block Write Read With ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Write With Auto Precharge /Block Write With Auto Precharge Precharge ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Bank Activating Write ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Write Recovering with Auto precharge /Block Write Recovering with Auto- precharge Refreshing ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) OPERATION COMMAND TABLE (Continued) Current CS RAS CAS WE DSF State Special Mode Register Setting ABBREVIATIONS : RA=Row Adress CA=Column Address Addr Command NOP (Return to original state after X X DESL ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) COMMAND TRUTH TABLE FOR CKE Current State CKE CKE CS n-1 n Self refresh Self refresh Recovery ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) COMMAND TRUTH TABLE FOR CKE (Continued) Current State CKE CKE CS n-1 n Both Banks Idle Any State Other Than Listed Above Notes:1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL TRUTH TABLE (Continued) Table 1. : Minimum Clock Latency Or Delay Time for 2 Bank Operation Second command (opposite bank) First command MRS t t RSC RSC SMRS t t RSC RSC ACTV (M) 1 BL-1 + READ t RSC *1 BL BL-1 READA + + RP *2 RSC * BL-1 WRIT + t RSC *1 BL-1 BL-1 WRITA t + RWL ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 Fig STATE DIAGRAM (One Bank Operation) MODE REGISTER SET SPECIAL MODE REGISTER SET BANK ACTIVE SUSPEND WRIT BWRIT CKE WRITE SUSPEND CKE\ WRITA BWRITA WRITE/BLOCK CKE WRITE WRITE SUSPEND PRECHARGE CKE\ POWER PRE or PALL ON POWER APPLIED DEFINITION OF ALLOWS Manual Input ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION SDRAM BASIC FUNCTION Five major differences between this SGRAM and conventional DRAMs are: synchronized operation, burst mode, mode register, write per bit, and block write. The synchronized operation is the fundamental difference. An SGRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory even if it has been using two clocks, RAS and CAS ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION (Continued) DATA INPUT AND OUTPUT (DQ Input data is latched and written into memory at the clock followed by a write command input. Data output is obtained by the following conditions followed by a read command input from the bank active command when t RAC t ; from the read command when t ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION (Continued) BURST MODE OPERATION AND BURST TYPE (continued) When the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0) ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION (Continued) PRECHARGE AND PRECHARGE OPTION (PRE, PALL) SGRAM memory is the same as DRAM, requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by Precharge command (PRE). With the precharge command, SGRAM will automatically be in idle state after precharge time (t ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION (Continued) BLOCK WRITE OPERATION (BWRIT, BWRITA) (Continued) The block write is always non-burst, independent of the burst length and burst type that has been programmed into the mode register. Back-to-back block write operation is allowed with the block write cycle time (t If WPB was enabled to the bank by ACTVM command, then write-per-bit masking of the color register data is enabled ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUNCTIONAL DESCRIPTION (Continued) POWER-UP INITIALIZATION The SGRAM internal condition after power-up will be undefined required to follow the following Power On Sequence to execute read or write operation. 1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 200 s. ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 Fig Basic Timing for Conventional DRAM vs Synchronous Graphic RAM <SGRAM> Active CLK H CKE t t CMS CMH CMS CMH RAS CAS WE DSF Address <Conventional DRAM> Row Adress Select RAS CAS DQ 24 Read/Write Read L : Write ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 CAPACITANCE Parameter Input Capacitance, Address Input Capacitance, Except for address I/O Capacitance RECOMMENDED OPERATING CONDITIONS (Referenced Parameter Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature Notes:1. Overshoot limit : V (max.)= Undershoot limit (min.)= –1.3 V with a pullsewidth 5 ns. IL Symbol Typ ...

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... Precharge Standby Current (Power Supply MB81G83222-010 Current) MB81G83222-012 MB81G83222-015 Active Standby Current MB81G83222-010 (Power Supply Current) MB81G83222-012 MB81G83222-015 Burst mode MB81G83222-010 Current MB81G83222-012 (Average Power Supply Current) MB81G83222-015 MB81G83222-010 Refresh Current #1 (Average Power MB81G83222-012 Supply Current) MB81G83222-015 MB81G83222-010 Refresh Current #1 (Average Power ...

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... Output in High-Z CAS latency=2 7 CAS latency=3 Output Hold Time Time between Refresh Transition Time Power Down Exit Time Symbol Conditions Self-Refresh; I CC6 CKE = V IL Block Write; I CC7 t = min. BWC MB81G83222-010 MB81G83222-012 Symbol Min. Max. Min — 17 3.5 — 3.5 — ...

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... — RWL t 20 — BWL t 20 — RRD t 20 — BWC t 20 — RSC Note 13 (Round off a whole number) Symbol MB81G83222-010 MB81G83222-012 MB81G83222-015 I 1 CKE I 2 DQZ I 0 DQD I 2 OWD I 0 DWD ROH BSH 3 ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 Notes:1. I depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; The CC specified values are obtained with the output open and no termination register initial pause (DESL or NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 Note: AC characteristics are measured in this condition. This load circuits are not applicable for V 30 Fig Example of AC Test Load Circuit R =50 1 Output C = LVTTL 1.4 V and ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 Fig TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME 2.0 V CLK 0 CKS Input (Control, Add. & Data) 2.4 V Output 0.4 V Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. Fig TIMING DIAGRAM, DELAY TIME for Power Down Exit CLK DON’ ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 CLK Input Command (Control) Note: This parameter is a limit value of the rising edge of the clock from one command input to next input the latency value from the rising edge of CKE. PDE Measurement reference voltage is 1.4 V. CLK RAS CAS DQ (Output) Note reference value ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 MODE REGISTER TABLE MODE REGISTER SET Op code Op-code Burst Read & Burst Write 1 Burst Read & Single Write Note: When A =1, burst length at Write is always one regardless of BL value ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ CLK CKE CLK (Internal) DQ (Read) DQ (Write) Notes: 1. The latency of CKE (l 2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output remain the same data. 3. During the write mode, data at the next clock of CSUS command is ignored. ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY CLK RAS t (min.) RCD CAS Row Address Address Note: CAS to CAS address delay can be one or more clock period. TIMING DIAGRAM-4 : DIFFERENT BANK ADDRESS INPUT DELAY CLK t (min.) RRD RAS t RCD CAS Row ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-5 : DQM - INPUT MASK AND OUTPUT DISABLE (@ BL=4) CLK DQM – Read Read) DQM – Write Write) TIMING DIAGRAM-6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK) CLK ACTV Command ACVTM 36 l (2clocks) DQZ Q1 Q2 Hi-Z l (same clock) DQD D3 D1 Masked t (min ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-7 : READ INTERRUPTED BY PRECHARGE (Example @ CL=2, BL=4) CLK Command Precharge DQ Command DQ Command DQ Command DQ Note: In case of CL=1, the clock. ROH In case of CL=2, the clock. ROH In case of CL=3, the clock. ROH l (2 clocks) ROH Hi-Z Q1 Precharge l (2 clocks) ROH Hi Precharge l (2 clocks) ROH ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-8 : READ INTERRUPTED BY BURST STOP (Example @ BL=Full Column) CLK Command (CL=1) DQ Qn- 2 Command (CL=2) DQ Qn- 2 Command (CL=3) DQ Qn- 2 Note: The BST command is applicable to terminated the full column burst operation. The selection of auto-precharge option is illegal during the full column burst operation except write command at BURST READ & ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-10 : WRITE INTERRUPTED BY DQM0~3 & PRECHARGE (Example @ CL=2) CLK Command t (min.) RWL DQM 0 to DQM 3 Last Masked DQ Data-In by DQM Note: The precharge command (PRE) should only be issued after the t TIMING DIAGRAM-11 : READ INTERRUPTED BY WRITE (Example @ CL= CLK READ Command DQM ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-12 : WRITE INTERRUPT BY READ TIMING (Example @ CL=3, BL>2) CLK Command DQM 0 to DQM 3 DQ Note: Read command can be asserted at the next cycle of write command. The write data after read command is masked by read command. CLK Command DQM 0 to DQM 3 Column Masking DQ Note: DQ inputs are used for column masking. (DQ=H : Write Enable, DQ=L : Masked) Write data is set by SMRS (Load Color Register) command ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-14 : WRITE PER BIT TIMING CLK t RRD ACTVM Command A (BA Note: WPB is available for the bank activated by ACTVM command. Mask Data (Mask enable/disable) is set by SMRS (Load Mask Register) command. TIMING DIAGRAM-15 : BLOCK WRITE TO READ/WRITE TIMING (Example @ CL= CLK ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-16 : READ WITH AUTO-PRECHARGE (Example @ CL=2, BL=2 Applied to same bank) CLK ACTV Command DQM 0 to DQM 3 DQ Note: Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length after READA command is asserted. TIMING DIAGRAM-17 : WRITE WITH AUTO-PRECHARGE ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-18 : BLOCK WRITE TO PRECHARGE TIMING CLK Command BWRIT DQM 0 to DQM 3 Column DQ Masking Note: The precharge command (PRE) should only be asserted after the t TIMING DIAGRAM-19 : BLOCK WRITE WITH AUTO-PRECHARGE(Applied to same bank) CLK t (min.)-t RAS BWL ACTV Command DQM 0 to ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-20 : AUTO-REFRESH TIMING CLK t RRD 1 Command REF A (BA) DON’T CARE 9 Notes: 1. All banks should be precharged prior to the first Auto-refresh command (REF). 2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. 3. Either NOP or DESL command should be asserted during t 4 ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-22 : BLOCK WRITE & SPECIAL MODE REGISTER SET TIMING CLK SMRS Command DQM 0 to DQM 3 Color or DQ Mask Notes: 1. Block Write command can be asserted after the t 2. Special Mode Register Set command can be asserted after t TIMING DIAGRAM-23 : SPECIAL MODE REGISTER SET TIMING ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 TIMING DIAGRAM-24 : MODE REGISTER SET TIMING CLK Command Address Note: The Mode Register Set command (MRS) should be only asserted after all banks have been precharged (min.) RSC MRS NOP or DESL ACTV ROW Mode Address ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 PACKAGE DIMENSIONS (Suffix: -PQ) 100-LEAD PLASTIC LEADED CHIP CARRIER .913 .016 (23.20 0.40) .787 .008 80 (20.00 0.20) 81 INDEX 100 LEAD No. 1 .0256 (0.65) TYP. .004 (0.10) .742 (18.85) REF. .850 .016 (21.60 0.40) 1995 FUJITSU LIMITED F100025S-2C (W) * This dimension is being changed. (CASE No.: LCC-100P-M15 .677 .016 .551 .008 “A” ...

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... MB81G83222-010/MB81G83222-012/MB81G83222-015 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U ...

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