LSI53C1010-66 LSI Computer Systems, Inc., LSI53C1010-66 Datasheet
LSI53C1010-66
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LSI53C1010-66 Summary of contents
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... TECHNICAL MANUAL LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller Version 2 ® S14049.A ...
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... LSI Logic officer is prohibited. Document DB14-000126-03, Third Edition (February 2001) This document describes the LSI Logic LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... Preface This book is the primary reference and technical manual for the LSI Logic LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller. This manual contains a complete functional description for the product and includes physical and electrical specifications. Audience This document was prepared for system designers and programmers who are using this device to design an Ultra160 SCSI port for PCI-based personal computers, workstations, servers or embedded applications ...
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... Appendix B, External Memory Interface Diagram contains several example interface drawings for connecting the LSI53C1010-66 to external ROMs. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U ...
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PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to ...
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Preface ...
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... PCI Functional Description 2.1.1 2.1.2 2.1.3 2.1.4 2.2 SCSI Functional Description 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Contents New Features in the LSI53C1010-66 ® Technology SCSI Performance PCI Performance Integration Ease of Use Flexibility Reliability Testability PCI Addressing PCI Bus Commands and Functions Supported Internal Arbiter PCI Cache Mode SCRIPTS Processor Internal SCRIPTS RAM ...
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... Parallel ROM Interface 2.4 Serial EEPROM Interface 2.4.1 2.4.2 2.5 Power Management 2.5.1 2.5.2 2.5.3 2.5.4 Chapter 3 Signal Descriptions 3.1 Signal Organization 3.2 Internal Pull-ups and Pull-Downs on LSI53C1010 Signals 3.3 PCI Bus Interface Signals 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 SCSI Bus Interface Signals 3.4.1 3.4.2 viii Contents Opcode Fetch Burst Capability Load and Store Instructions JTAG Boundary Scan Testing ...
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General Purpose I/O (GPIO) Signals 3.5.1 3.5.2 3.6 Flash ROM and Memory Interface Signals 3.7 Test Interface Signals 3.8 Power and Ground Signals 3.9 MAD Bus Programming Chapter 4 Registers 4.1 PCI Configuration Registers 4.2 SCSI Registers 4.3 SCSI ...
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... Typical LSI53C1010-66 System Application LSI53C1010-66 Block Diagram DMA FIFO Sections LSI53C1010 Host Interface SCSI Data Paths Regulated Termination for Ultra160 SCSI Determining the Synchronous Transfer Rate Interrupt Routing Hardware Using the LSI53C1010 Chained Block Move Instruction LSI53C1010-66 Functional Signal Grouping Single Transition Transfer Waveforms 5-38 5-40 5-41 6-1 6-7 6-10 ...
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Double Transition Transfer Waveforms (XCLKS Examples) 4.3 Double Transition Transfer Waveforms (XCLKH Examples) 5.1 SCRIPTS Overview 5.2 Block Move Instruction - First Dword 5.3 Block Move Instruction - Second Dword 5.4 Block Move Instruction - Third Dword 5.5 First ...
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... Target Asynchronous Send Target Asynchronous Receive Initiator and Target ST Synchronous Transfer Initiator and Target DT Synchronous Transfer LSI53C1010-66 329 BGA Chip - Top View LSI53C1010-66 329 Ball Grid Array (Bottom view) LSI53C1010-66 329 BGA Mechanical Drawing 16 Kbyte Interface with 200 ns Memory 64 Kbyte Interface with 150 ns Memory ...
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... Bits Used for Parity/CRC/AIP Control and Generation 2.5 SCSI Parity Errors and Interrupts 2.6 SCF Divisor Values 2.7 Parallel ROM Support 2.8 Default Download Mode Serial EEPROM Data Format 2.9 Power States 3.1 LSI53C1010 Internal Pull-ups and Pull-downs 3.2 System Signals 3.3 Address and Data Signals 3.4 Interface Control Signals 3.5 Arbitration Signals 3.6 Error Reporting Signals 3.7 Interrupt Signals 3 ...
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Contents LVD Receiver SCSI Signals—SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, ...
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... Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6.49 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6.50 Ultra160 SCSI Transfers 160.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6.51 Alphanumeric List by BGA Position 6.52 Alphanumeric List by Signal Name A.1 LSI53C1010 PCI Register Map A.2 LSI53C1010 SCSI Register Map Contents 6-45 6-48 6-50 6-56 6-58 6-60 6-61 6-62 6-63 6-63 6-64 6-64 6-65 6-65 ...
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Contents ...
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... Chapter 1 Introduction This chapter provides a general overview on the LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller. This chapter contains the following sections: Section 1.1, “General Description” Section 1.2, “Benefits of Ultra160 SCSI” Section 1.3, “Benefits of SureLINK (Ultra160 SCSI Domain Validation)” ...
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... Parity, and 68 Pin Control Signals Wide SCSI Connector and Terminator LVDlink™ technology is the LSI Logic implementation of Low Voltage Differential (LVD). LVDlink transceivers allow the LSI53C1010-66 to perform either Single-Ended (SE) or LVD transfers. The LSI53C1010 1-2 Introduction Memory Address/Data LSI53C1010 64-Bit / 66MHz A_GPIO/[1:0] ...
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... Ultra160 SCSI standards. It implements multithreaded I/O algorithms with minimum processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. typical LSI53C1010 system application. Figure 1.2 Typical LSI53C1010-66 System Application PCI Bus PCI Bus Interface Controller Central ...
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... New Features in the LSI53C1010-66 The LSI53C1010 is functionally similar to the LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller, with additional features and benefits. Following is a list of new LSI53C1010-66 features: Supports 66 MHz PCI Complies with PCI Rev. 2.2 specification Supports Ultra160 DT clocking for data transfers up to 160 Mbytes/s ...
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... CRC-32. CRC is guaranteed to detect all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range. AIP is also supported by the LSI53C1010, protecting all nondata phases, including command, status, and messages. CRC, along with AIP, provides end-to-end protection of the SCSI I/O. ...
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... SCSI. LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity. For backward compatibility to existing SE devices, the LSI53C1010 features universal LVDlink transceivers that support LVD SCSI and SE SCSI. This allows use of the LSI53C1010 in both legacy and Ultra160 SCSI applications. 1-6 Introduction ...
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... TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute. 1.6 Summary of LSI53C1010-66 Benefits This section provides a summary of the LSI53C1010 features and benefits. It contains information on SCSI Performance, PCI Performance, Integration, Ease of Use, Flexibility, Reliability, and Testability. ...
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... SCSI Performance The LSI53C1010-66: Performs wide, Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s on each SCSI channel for a total of 320 Mbytes/s using DT clocking. Supports CRC checking and generation in DT phases. Protects nondata phases with AIP. Supports Domain Validation: – – – ...
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... Supports 32-bit or 64-bit word data bursts with variable burst lengths. Prefetches Dwords of SCRIPTS instructions. Bursts SCRIPTS opcode fetches across the PCI bus. Summary of LSI53C1010-66 Benefits Can function in a 32-bit or 64-bit PCI slot Operates MHz Supports Dual Address Cycle (DAC) generation for all SCRIPTS ...
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... Complies with PCI Bus Power Management Specification Revision 1.1. Complies with PC99. 1.6.3 Integration The following features ease integration of the LSI53C1010 into a system. Dual channel Ultra160 SCSI PCI multifunction controller. Integrated LVD transceivers. Full 32-bit or 64-bit PCI DMA bus master. Memory-to-Memory Move instructions allow use as a third-party PCI bus DMA controller ...
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... Fetch, Master, and Memory Access control pins. Separate SCSI and system clocks. SCSI clock quadrupler bits enable Ultra160 SCSI transfer rates with a 40 MHz SCSI clock input. Selectable IRQ pin disable bit. Compatible with 3.3 V and 5 V PCI. Summary of LSI53C1010-66 Benefits 1-11 ...
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... Power and ground isolation of I/O pads and internal chip logic. TolerANT technology provides: – – 1.6.7 Testability The following features enhance the testability of the LSI53C1010: All SCSI signals accessible through programmed I/O. SCSI bus signal continuity checking. Support for single step mode operation. JTAG boundary scan. ...
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... Chapter 2 Functional Description This chapter provides a functional description of the LSI53C1010-66. This chapter is divided into the following sections: Section 2.1, “PCI Functional Description” Section 2.2, “SCSI Functional Description” Section 2.3, “Parallel ROM Interface” Section 2.4, “Serial EEPROM Interface” Section 2.5, “Power Management” ...
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... SCSI Function A Bus Wide Ultra160 SCSI Bus The LSI53C1010-66 has two wide Ultra160 SCSI channels in a single package. Each SCSI channel (A and B) incorporates an independent DMA FIFO and a separate internal 8 Kbyte SCRIPTS RAM. 2.1 PCI Functional Description The LSI53C1010-66 implements two PCI to Wide Ultra160 SCSI controllers in a single package. This confi ...
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... PCI Configuration Register Map. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the LSI53C1010, the upper 24 bits of the address are selected. On every access, the LSI53C1010 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If the upper 24 bits match, the access is designated for the LSI53C1010. The low order eight bits defi ...
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... I/O Space The PCI specification defines I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C1010. which 256-byte I/O area this device occupies. 2.1.1.3 Memory Space The PCI specification defines memory space as a contiguous 64-bit memory address that is shared by all system resources. ...
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... I/O Write Command The LSI53C1010 uses the I/O Write command to write data to an agent mapped in the I/O address space. When decoding I/O cycles, the LSI53C1010-66 decodes the lower 32 address bits and ignores the upper 32 address bits. PCI Functional Description PCI Bus Commands and Encoding Types (Cont.) Reserved Confi ...
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... Memory Address Space. The target may perform an anticipatory read if such a read produces no side effects. 2.1.2.7 Memory Write Command The LSI53C1010 uses the Memory Write command to write data to an agent mapped in the Memory Address Space. When the target returns “ready”, it assumes responsibility for data coherency, which includes ordering. 2.1.2.8 Confi ...
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... The maximum allowable burst size is determined from the (DMODE) 2.1.2.11 Dual Address Cycles (DACs) Command When 64-bit addressing is required, the LSI53C1010 performs DACs, per the PCI 2.2 specification. If any of the selector registers contain a nonzero value, a DAC is generated. PCI Functional Description ...
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... The Read Line function in the LSI53C1010 takes advantage of the PCI 2.2 specification regarding issuance of this command. If the cache mode is disabled, no Read Line commands are issued. ...
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... The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C1010 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. ...
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... PCI bus. An internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for PCI bus access. There are two independent bus mastering functions inside the LSI53C1010, one for each of the SCSI functions. 2-10 ...
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... PCI bus. This ensures that no function is starved for access to the PCI bus. 2.1.4 PCI Cache Mode The LSI53C1010 supports the PCI specification for an 8-bit Size (CLS) Line Size (CLS) nonaligned addresses corresponding to cache line boundaries. In ...
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Table 2.2 G 2.1.4.1 Enabling Cache Mode To enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any PCI master operation, the following conditions must be met: The ...
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Not only must the above four conditions be met in order for the cache logic to control the type of PCI cache command that is issued, proper alignment is also necessary during write operations. If these conditions are not met ...
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Memory Read Multiple command is issued transfer does not cross a Dword or cache boundary or if cache mode is not enabled a Memory Read command is issued. 2.1.4.4 Memory Write Caching Memory Writes are aligned ...
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Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords MRL (6 bytes MRL (13 bytes MRM (16 bytes byte MRM (5 ...
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Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords Read Example ...
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Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords bytes (13 bytes (17 bytes bytes ...
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Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords Write Example ...
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... Ultra160 SCSI requirements. between the LSI53C1010 modules. The LSI53C1010 offers low level register access or a high level control interface. Like first generation SCSI devices, the LSI53C1010 is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures ...
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... SCRIPTS instructions. These registers are described in detail in 2.2.2 Internal SCRIPTS RAM The LSI53C1010 has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM for each SCSI function. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. ...
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... SCSI SCRIPTS. For more information on the SCSI SCRIPTS instructions supported by the LSI53C1010, see SCRIPTS Instruction Set.” 2.2.3 64-Bit Addressing in SCRIPTS The PCI interface for the LSI53C1010 provides 64-bit address and data capability in the initiator mode. The chip can also respond to 64-bit addressing in the target mode. SCSI Functional Description Chip Control Zero (CCNTL0) register ...
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... LSI53C1010 is not performing an EEPROM autodownload. The CON (Connected) bit in the LSI53C1010 is connected to the SCSI bus either as an initiator or a target. This happens after the LSI53C1010 has successfully completed a selection or when it has successfully responded to a selection or reselection. The CON bit is also set when the LSI53C1010 wins arbitration in low level mode ...
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... Designing an Ultra160 SCSI System Software modifications are needed to take advantage of the Ultra160 speed in the LSI53C1010. Since Ultra160 SCSI is based on existing SCSI standards, it can use existing drivers if they are able to negotiate for Ultra160 synchronous transfer rates. Also, the target device must be able to communicate at Ultra160 speed ...
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CRC – CRC is the error detecting code used in Ultra160 SCSI. Four bytes are transferred with data to increase the reliability of data transfers. CRC is used in the DT Data-In and DT Data-Out phases only. Because CRC is ...
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Parallel Protocol Request CRC, Sync/Wide, DT, Quick Arbitration and Selection (QAS), and “information units” are negotiated with a new SCSI extended message: Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Transfer ...
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Note: Note: Protocol Options (Byte 7) – A bus or device reset, power cycle, or change between LVD/SE modes invalidates these settings. A renegotiation resets the Protocol Options. QAS_REQ 2.2.5.3 Asynchronous Information Protection (AIP) The ...
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... SCSI Interrupt Status Zero (SIST0) CRC, or AIP errors are present. The AIPERR bit in the (AIPCNTL0) 2.2.5.4 Register Considerations The following is a summary of the registers and bits required to enable Ultra160 SCSI on the LSI53C1010 device. The PCI The PCI it requires the bus every 4.5 s. The – ...
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The – – The – The – The – – – The – 2-28 Functional Description Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor), select the divisor of the SCLK frequency. The SCLK is divided before its presentation ...
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Bit 6, AIPCKEN (AIP Checking Enable), is set to enable checking of the upper byte lane of protection information during Command, Status, and Message Phases. – Bits [5:4] are reserved. – Bit 3, XCLKH_DT (Extra Clock of Data Hold ...
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... SPI-3 specification. Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the LSI53C1010 to not check for a CRC request prior to a phase change on the SCSI bus. This condition creates a SCSI error condition and makes the device noncompliant with the SPI-3 specifi ...
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... The – 2.2.5.5 Using the SCSI Clock Quadrupler The LSI53C1010 can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user-selectable with bit settings in the Test Three power-on or reset, the quadrupler is disabled and powered down. Follow these steps to use the clock quadrupler: 1 ...
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... PCI cache commands Memory Read Line and Memory Read Multiple, if PCI caching is enabled. Note: To ensure the LSI53C1010 always operates from the current version of the SCRIPTS instruction, the contents of the prefetch unit may be flushed under certain conditions. The contents of the prefetch unit are automatically fl ...
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... Load and Store instructions, refer to SCRIPTS Instruction Set.” SCSI Functional Description (DMA Control (DCNTL) register (0x38) causes the LSI53C1010 to burst in the first two This feature is only useful if Prefetching is disabled. This feature is only useful if fetching SCRIPTS instructions from main memory. Due to the short access time of SCRIPTS RAM, burst opcode fetching is not necessary when fetching instructions from SCRIPTS RAM ...
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... SCRIPTS RAM must first be written before being read in order to initialize SCRIPTS RAM parity SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt is signaled. The LSI53C1010 supports CRC checking and generation in DT phases and CRC checking and generation during DT Data Transfers. The new CRC registers are: Control Zero (CRCD) ...
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... Data Latch (SIDL) This bit enables parity checking during PCI master data phases. This bit is set when the LSI53C1010 PCI master, detects a target device signaling a parity error during a data phase. By clearing this bit, a Master Data Parity Error does not ...
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... This bit is set to cause the device not to check for a CRC request prior to a phase change on the SCSI bus. This condition normally causes a SCSI error condition. Note: Setting this bit makes the LSI53C1010 noncompliant to the SPI-3 specification. Do not set this bit under normal operating conditions. ...
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... DMA transfers. The FIFO allows the LSI53C1010 to support 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12 SCSI Data Paths The data path through the LSI53C1010 is dependent on whether data is moved into or out of the chip and whether the SCSI data transfer is asynchronous or synchronous. ...
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... Figure 2.3 LSI53C1010 Host Interface SCSI Data Paths Asynchronous Asynchronous SCSI Send SCSI Receive PCI Interface PCI Interface DMA FIFO DMA FIFO SODL Register SIDL Register SCSI Interface SCSI Interface 2.2.12.1 Asynchronous SCSI Send To determine the number of bytes remaining in the DMA FIFO when a phase mismatch occurs, read the register ...
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... DMA FIFO by setting bit 2 (CLF) in clear the SCSI FIFO by setting bit 1 (CSF) in and retry the I/O. 2.2.13 SCSI Bus Interface The LSI53C1010 performs SE and LVD transfers. SCSI Functional Description register. This 16-bit, read only register contains the and retry the I/O. SCSI Wide Residue (SWIDE) is set, then the SWIDE register contains a and retry the I/O ...
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... Functional Description register, and bit 5 (previously DIF), of the register, are reserved. The A_DIFFSENS or pull-up resistor to the terminator power pull-down resistor to ground. If the LSI53C1010 is used in a design with an 8-bit SCSI bus, all 16 data lines must be terminated. SCSI SCSI Test Figure 2.4 shows an active ...
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... Set Initiator instruction or the target SCRIPTS issues a Set Target instruction. The Selection and Reselection Enable bits ID (SCID) the LSI53C1010 to respond as an initiator target. If only selection is enabled, the LSI53C1010 cannot be reselected as an initiator. Status SCSI Functional Description Regulated Termination for Ultra160 SCSI ...
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... Ultra160 SCSI for Ultra2 SCSI for Ultra SCSI, 100 ns for Fast SCSI, and 200 ns for SCSI-1. Synchronous data transfer rates are controlled by bits in two different registers of the LSI53C1010. Following is a brief description of these bits and the method used to determine the data transfer rate. 2.2.15.1 ...
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... This bit impacts DT and ST transfers as it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010 receives outbound REQs, ACKs, or data. Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT transfer edge), adds a clock of data setup to synchronous DT SCSI transfers on the DT edge ...
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... The synchronous send rate, in units of megatransfers/s, can be calculated using the following formula: Send Rate (DT) = Send Rate (ST) To configure the LSI53C1010 for Ultra160 DT transfers, perform the following steps: Step 1. Enable the SCSI Clock Quadrupler – The LSI53C1010 can 2-44 Functional Description Input Clock Rate Receive Rate (DT) --------------------------------------------- - (Megatransfers/s) = ...
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... An example of configuring the Ultra160 SCSI transfer speed is: 1. Set SCNTL3 to 0x18. 2. Set SXFER to 0x3E. 3. Set SCNTL4 to 0x80. These settings program the LSI53C1010 SCSI clocks to send and receive at 160 MHz with a synchronous SCSI offset of 0x3E. SCSI Functional Description SCSI Test 2-45 ...
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... The SCRIPTS processors in the LSI53C1010 perform most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C1010. 2.2.16.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts ...
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... SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is normally routed to INTB/, but can be routed to INTA pull-up is connected to MAD[4]. See additional information. 2.2.16.2 Registers The registers in the LSI53C1010 used for detecting or defining interrupts are Interrupt Status Zero Interrupt Status Zero Status (DSTAT), SCSI Interrupt Enable Zero ...
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... Interrupt Status Zero (SIST0) clear the CRC Error bit (bit 7) in the register. If the LSI53C1010 is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could remain in the DMA FIFO. To determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE) ...
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... DMA Interrupt Enable (DIEN) DMA Status Section 2.2.16.4, “Masking.” and one or more bits in DMA Status register. The CSF bit register. register. Since the LSI53C1010 register, is purely a status bit; it and and register is the interrupt enable (DSTAT). Clearing the All DMA interrupts are fatal. ...
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... CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C1010 is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or handshake-to-handshake timers expire. These interrupts are not needed for events that occur during high level SCRIPTS operation ...
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... Interrupt Status Zero (ISTAT0) the INTA/ (or INTB/) pin. 2.2.16.5 Stacked Interrupts The LSI53C1010 stacks interrupts, if they occur, one after the other. If the SIP or DIP bits in the (first level), then there is already at least one pending interrupt. Any future interrupts are stacked in extra registers behind the ...
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... These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C1010 attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction since it is updated when the current instruction is fetched ...
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... All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C1010. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used. 1. Read 2. If the INTF bit is set, write one to clear this status. ...
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... Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the LSI53C1010. In order to be compatible with RAID upgrade products and the LSI53C1010, the following requirements must be met: When a RAID upgrade card is installed in the upgrade slot, interrupts ...
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... If this restriction is not acceptable, additional buffer logic must be implemented on the mainboard. As long as the interrupt routing requirements stated above are satisfied, a mainboard designer could implement this design with external logic. Figure 2.6 Interrupt Routing Hardware Using the LSI53C1010 + LSI53C1010 2 ...
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... BIOS and assumes the operating system uses PCI BIOS calls when searching for PCI devices. 2.2.18 Chained Block Moves Since the LSI53C1010 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI ...
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Moves five bytes from address 0x03 in the host memory to the SCSI bus. Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the SCSI core (in the lower byte of the SODL register for asynchronous ...
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Chained Block Move instruction. Under this condition the high-order byte is not transferred out the DMA channel to memory. Instead stored in the Residue (SWIDE) The hardware uses ...
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... SCSI bus recommended that all Block Move instructions be Chained Block Moves. 2.3 Parallel ROM Interface The LSI53C1010 supports Mbyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add-in PCI cards. Both functions of the device share the ROM interface. ...
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... HCT external components to be used. Pull-up resistors on the 8-bit bidirectional memory bus at power-up determine the memory size and speed. The LSI53C1010 senses this bus shortly after the release of the Reset signal and configures the Expansion ROM Base Address register and the memory cycle state machines for the appropriate conditions. ...
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... MAD[2]. If the external memory interface is not used, MAD[3:1] should be pulled HIGH. The LSI53C1010 allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI configuration space. For more information on how this works, refer to the PCI specifi ...
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... PCI specification, with a default value of 0x1000 and 0x1000 respectively. 2.5 Power Management The LSI53C1010 complies with the PCI Bus Power Management Interface Specification, Revision 1.1, in which the D0, D1, D2, and D3 are defined the maximum powered state, and D3 is the minimum powered state ...
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... The LSI53C1010 is fully functional in this state. 2.5.2 Power State D1 Power state lower power state than D0. A function in this state places the LSI53C1010 core in the snooze mode and disables the SCSI CLK. In the snooze mode, a SCSI reset does not generate an IRQ/ signal. ...
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... D0 by applying V Power state lower power level than power state D2. A function in this state places the LSI53C1010 core in the coma mode. Furthermore, the function's soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus. In ...
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... Test Interface Figure 3.1 slash (/) at the end of a signal name indicates that active LOW signal. When the slash is absent, the signal is active at a HIGH voltage. LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller illustrates the signals, their grouping, and their I/O direction. A 3-1 ...
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The PCI Interface contains many functional groups of signals. The SCSI Bus Interface contains two functional groups of signals. There are five signal type definitions I/O T/S S/T/S Figure 3.1 package drawings are available in 3-2 Signal Descriptions ...
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... Figure 3.1 LSI53C1010-66 Functional Signal Grouping System Address and Data Interface Control PCI Bus Interface Arbitration Error Reporting Interrupt SCSI Function A GPIO GPIO Interface SCSI Function B GPIO Flash ROM and Memory Interface Signal Organization LSI53C1010-66 CLK SCLK ENABLE66 M66EN RST/ A_SD[15:0]/ A_SDP[1:0]/ ...
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... Internal Pull-ups and Pull-Downs on LSI53C1010 Signals Several LSI53C1010 signals use internal pull-ups or pull-downs. Table 3.1 pull-downs. Table 3.1 LSI53C1010 Internal Pull-ups and Pull-downs Pin Name INTA/, INTB/, ALT_INTA/, ALT_INTB/ ENABLE66, INT_DIR, M66EN, TCK, TDI, TEST_RST/, TMS AD[63:32], C_BE[7:4]/, PAR64 GPIO[4:0] MAD[7:0] TEST_PD, SCAN_MODE, TEST_HSC 1 ...
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PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: Data Signals, Reporting 3.3.1 System Signals Table 3.2 Table 3.2 System Signals Name Bump Type CLK H3 I ENABLE66 ...
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Address and Data Signals Table 3.3 Table 3.3 Address and Data Signals Name Bump AD[63:0] Y5, AB5, AC5, AA6, Y6, AB6, AC6, AA7, AB7, AC7, AA8, Y8, AB8, AC8, AA9, Y9, AB9, AC9, AA10, Y11, AB10, AC10, AA11, AC11, ...
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Table 3.3 Address and Data Signals (Cont.) Name Bump PAR64 AA5 3.3.3 Interface Control Signals Table 3.4 Table 3.4 Interface Control Signals Name Bump Type ACK64/ AB1 S/T PCI Acknowledge 64-bit transfer is driven by the current bus ...
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Table 3.4 Interface Control Signals (Cont.) Name Bump Type STOP/ R2 S/T PCI Stop indicates that the selected target is requesting the DEVSEL/ R1 S/T PCI Device Select indicates that the driving device has IDSEL L3 ...
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Error Reporting Signals Table 3.6 Table 3.6 Error Reporting Signals Name Bump Type Strength Description PERR/ R4 S/T PCI Parity Error may be pulsed active by an agent that detects SERR PCI System ...
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... SCSI Test One (STEST1) information about disabling this interrupt in a RAID environment. At power-up, this interrupt can be rerouted to INTA/ using the INTA/ enable sense resistor (pull-up on MAD4). This causes the LSI53C1010 to program the SCSI Function B PCI Interrupt Pin (IP) SCSI Test One (STEST1) register to 0x01. ...
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Table 3.7 Interrupt Signals (Cont.) 1 Name Bump Type INT_DIR See Register 0x4D, SCSI Test One (STEST1) these signals. 3.4 SCSI Bus Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the ...
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SCSI Function A Signals This section describes the signals for the SCSI Function A Signals group. Table 3.9 describes the SCSI Function A Control Signals. Table 3.9 SCSI Function A Signals Name Bump A_SD[15:0] B5, C5, B4, C4, D19, ...
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Table 3.9 SCSI Function A Signals (Cont.) Name Bump A_DIFFSENS A20 SCSI Bus Interface Signals Type Strength Description I N/A SCSI Function A Differential Sense pin detects the present mode of the SCSI bus when connected to the DIFFSENS signal ...
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Table 3.10 SCSI Function A Control Signals 1 Name Bump Type SCSI Function A Control includes the following signals: A_SC_D C15 I/O A_SC_D+ A16 A_SI_O B17 A_SI_O+ C17 A_SMSG C14 A_SMSG+ A15 A_SREQ C16 A_SREQ+ A17 A_SACK C13 A_SACK+ A14 ...
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SCSI Function B Signals This section describes the SCSI Function B Signals group. describes the SCSI Function B Signals and SCSI Function B Control Signals. Table 3.11 SCSI Function B Signals Name Bump B_SD[15:0] F21, E22, E21, D22, Y22, ...
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Table 3.11 SCSI Function B Signals (Cont.) Name Bump B_DIFFSENS Y21 3-16 Signal Descriptions Type Strength Description I N/A SCSI Function B Differential Sense pin detects the present mode of the SCSI bus when connected to the DIFFSENS signal on ...
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Table 3.12 SCSI Function B Control Signals 1 Name Bump Type SCSI Function B Control includes the following signals: B_SC_D T20 I/O B_SD_D+ T21 B_SI_O V22 B_SI_O+ V20 B_SMSG R20 B_SMSG+ R21 B_SREQ U21 B_SREQ+ V23 B_SACK N20 B_SACK+ P21 ...
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... General Purpose I/O (GPIO) Signals This section describes the GPIO signals on the LSI53C1010. Each SCSI function is associated with a separate set of GPIO signals. 3.5.1 SCSI Function A GPIO Signals Table 3.13 Table 3.13 SCSI Function A GPIO Signals Name Bump Type A_GPIO0_ AB16 I/O FETCH/ A_GPIO1_ Y16 I/O MASTER/ A_GPIO2 ...
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... MAD7 pin to serve as the clock signal for the serial EEPROM interface. If bit 7 of the (GPCNTL) register is set, this pin is driven LOW when the LSI53C1010 is the bus master SCSI Function B General Purpose I/O pin 2. This pin powers input SCSI Function B General Purpose I/O pin 3 ...
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... Memory Address Strobe 1. This pin latches in the most significant address byte (bits [15:8 external EPROM or flash memory. Since the LSI53C1010 moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops that assemble 20-bit address for the external memory ...
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... Memory Output Enable. This pin is used as an output enable signal to an external EPROM or flash memory during read operations also used to test the connectivity of the LSI53C1010 signals in the “AND-tree” test mode. I N/A Test Clock. This pin provides the clock for the JTAG test logic ...
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Power and Ground Signals Table 3.17 Table 3.17 Power and Ground Signals 1 Name Bump V IO C3, C21, D4, SS_ D12, D20, K10–14, L10–14, M4, M10–14, M20, N10–14, P10–14, Y4, Y12, Y20, AA3, AA21 V IO D7, D10, ...
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Table 3.17 Power and Ground Signals (Cont.) 1 Name Bump RBIAS M21 NC A1, A13, A23, B13, B16, B21, D16, P22, P23, U22, U23, AB22 1. The I/O driver pad rows and digital core have isolated power supplies as indicated ...
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MAD[4], INTA/ routing enable – Placing a pull-up resistor on this pin causes SCSI Function B interrupt requests to appear on the INTA/ pin, along with SCSI Function A interrupt requests, instead of on INTB/. Placing a pull-up resistor on ...
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... Table 4.1 LSI53C1010. All PCI-compliant devices, such as the LSI53C1010, support Device PCI-compliant registers is optional. In the LSI53C1010, registers that are LSI53C1010-66 PCI to Dual Channel Ultra160 SCSI Multifunction Controller shows the PCI configuration registers implemented in the ID, Command, and Status registers. Support of other Interrupt Pin (IP) register ...
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... Only those registers and bits that are currently supported by the LSI53C1010 are described in this chapter. Do not access bits marked as Reserved. Table 4.1 PCI Configuration Register Map 31 Device ID Status Class Code (CC) ...
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... Registers: 0x02–0x03 Device ID Read Only DID Device ID This 16-bit register identifies the particular device. The LSI53C1010-66 Device ID is 0x0021. Registers: 0x04–0x05 Command Read/Write The SCSI Command register provides coarse control over a device’s ability to generate and respond to PCI cycles ...
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... Reserved Enable Bus Mastering This bit controls the ability of the LSI53C1010 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1010 to behave as a bus master ...
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... DPE Detected Parity Error (from Slave) This bit is set by the LSI53C1010 upon the detection of a data parity error, even if data parity error handling is disabled. SSE Signaled System Error This bit is set whenever the device asserts the SERR/ signal ...
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... Fast Back to Back Capable This bit is zero. Reserved 66 MHz Capable When set, this bit indicates that the LSI53C1010 is capable of 66 MHz PCI operation. This bit is controlled by the ENABLE66 pin, which has a static pull-up. New Capabilities This bit is set to indicate a list of extended capabilities such as PCI Power Management ...
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Registers: 0x09–0x0B Class Code (CC) Read Only Register: 0x0C Cache Line Size (CLS) Read/Write 7 0 CLS PCI Configuration Registers Class Code ...
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... Header Type This 8-bit register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. Since the LSI53C1010 is a multifunction controller the value of this register is 0x80 ...
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... Base Address Register Zero - I/O This base address register is used to map the operating register set into I/O space. The LSI53C1010 requires 256 bytes of I/O space for this base address register. Bit 0 is hardwired to one. Bit 1 is reserved and returns a zero on all reads. All other bits are used to map the device into I/O space ...
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... SCRIPTS RAM into memory space and represents the lower 32 bits of the memory address. Bits [12:0] are hardwired to 0b0000000000100. The default value of this register is 0x00000004. The LSI53C1010 requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 specification. 0 ...
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... SCRIPTS RAM into memory space and represents the upper 32 bits of the memory address. The default value of this register is 0x00000000. The LSI53C1010 requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 specification. ...
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Registers: 0x2C–0x2D Subsystem Vendor ID (SVID) Read Only SVID 4-12 Registers SVID If MAD7 is HIGH MAD7 is LOW Subsystem Vendor ...
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Registers: 0x2E–0x2F Subsystem ID (SID) Read Only SID Subsystem ID This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device ...
Page 130
... Expansion ROM Base Address (ERBA) ones and then reading back the register. The SCSI functions of the LSI53C1010 respond with zeros in all don’t care locations. The least significant one (1) that remains represents the binary version of the external memory size ...
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Register: 0x34 Capabilities Pointer (CP) Read Only Registers: 0x35–0x37 Reserved This register is reserved. Registers: 0x38–0x3B Reserved This register is reserved. PCI ...
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Register: 0x3C Interrupt Line (IL) Read/Write Register: 0x3D Interrupt Pin (IP) Read Only Note: 4-16 Registers Interrupt Line This register is used to communicate interrupt line routing ...
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... Min_Gnt This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 s. The LSI53C1010 sets this register to 0x11. Register: 0x3F Max_Lat (ML) ...
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... PMES D2S D1S AUX_C PME_Support Bits [15:11] define the power management states in which the LSI53C1010 will assert the PME pin. These bits are all set to zero because the LSI53C1010 does not provide a PME signal. CID NIP ...
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... Bit 3 is cleared because the LSI53C1010 does not provide a PME pin. VER[2:0] Version These three bits are set to 0b010 to indicate that the LSI53C1010 complies with Revision 1.1 of the PCI Power Management Interface Specification. Registers: 0x44–0x45 Power Management Control/Status (PMCSR) Read/Write ...
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... The LSI53C1010 always returns zero for this bit to indicate that PME assertion is disabled. Reserved Power State Bits [1:0] are used to determine the current power state of the LSI53C1010. They are used to place the LSI53C1010 in a new power state. Power states are defined as: 0b00 D0 0b01 D1 0b10 D2 0b11 D3 hot See the Section 2.5, “ ...
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... Register: 0x47 Data Read Only DATA Data This register provides an optional mechanism for the function to report state-dependent operating data. The LSI53C1010 always returns 0x00. PCI Configuration Registers DATA [7:0] 4-21 ...
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... Updated Address Instruction Address (IA), SCSI Byte Count The only registers that the host CPU can access while the LSI53C1010 is executing SCRIPTS are the Zero (ISTAT0), Interrupt Status One (MBOX0), and Mailbox One (MBOX1) access other registers interfere with the operation of the chip ...
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Table 4.2 SCSI Register Map 31 SCNTL3 SCNTL2 GPREG SDID SBCL SSID SSTAT2 SSTAT1 MBOX1 MBOX0 CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SBR SIST1 SIST0 GPCNTL Reserved RESPID1 RESPID0 STEST3 STEST2 CSO STEST4 CCNTL1 CCNTL0 CCNTL3 CCNTL2 SCRATCH C–SCRATCH R ...
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... Full arbitration, selection/reselection Simple Arbitration 1. The LSI53C1010 SCSI function waits for a bus free condition to occur asserts SBSY/ and its SCSI ID, contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device, the LSI53C1010 SCSI function deasserts SBSY/, deasserts its ID, and sets the Lost Arbitration ...
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... Time-Out bit is set in the (SIST1) START Start Sequence When this bit is set, the LSI53C1010 starts the arbitration sequence indicated by the Arbitration Mode bits. The Start Sequence bit is accessed directly in low level mode; during SCSI SCRIPTS operations, this bit is controlled by the SCRIPTS processor. Do not start an arbitration ...
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... SCSI Interrupt Status Zero (SIST0) register is set and an interrupt may be generated. If the LSI53C1010 SCSI function is operating in the initiator mode and a parity error or CRC error is detected, SATN/ can optionally be asserted, but the transfer continues until the target changes phase or the block move in which the parity error was detected completes ...
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... The SATN/ signal is asserted before deasserting SACK/ during the byte transfer with the parity error. Also set the Enable Parity/CRC/AIP Checking bit for the LSI53C1010 SCSI function to assert SATN/ in this manner. A parity error or CRC error is detected on data received from the SCSI bus. ...
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... Reserved Assert SCSI Data Bus When this bit is set, the LSI53C1010 SCSI function drives the contents of the SCSI Output Data Latch (SODL) register onto the SCSI data bus. When the LSI53C1010 SCSI function is an initiator, the SCSI I/O signal must be inactive to assert the SODL contents onto the SCSI bus. ...
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... Connected This bit is automatically set any time the LSI53C1010 SCSI function is connected to the SCSI bus as an initiator target set after the LSI53C1010 SCSI function successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode ...
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... SCSI bus not acceptable the Bus Free phase immediately following the arbitration phase possible to perform a low level selection instead. The abort completes because the LSI53C1010 SCSI function loses arbitration. This is detected by the clearing of the Immediate Arbitration bit. Do not use the Lost Arbitration bit bit 3) to detect this condition ...
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To SCSI Control Two expects a disconnect to occur, normally prior to sending an Abort, Abort Tag, Bus Device Reset, Clear Queue or Release Recovery message, or before deasserting SACK/ after ...
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WSR Register: 0x03 SCSI Control Three (SCNTL3) Read/Write This register is automatically loaded when a Table Indirect Select or Reselect SCRIPTS instruction is executed. R SCF[2:0] 4-32 Registers Wide SCSI Receive When read, this bit returns the ...
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... SRE Reserved RRE Enable Response to Reselection When this bit is set, the LSI53C1010 SCSI function is enabled to respond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) One (RESPID1) automatically reconfigure itself to the initiator mode as a result of being reselected. SRE ...
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... SCSI data in either the initiator or target mode. Table 4.3 combinations and their relationship to the synchronous data offset used by the LSI53C1010 SCSI function. These bits determine the LSI53C1010 SCSI function’s method of transfer for ST/DT Data-In and ST/DT Data-Out phases only; all other information transfers occur asynchronously ...
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A value these bits program the device to perform asynchronous transfers. A value of 1 during DT transfers is illegal and will result in data corruption. Table 4.3 Maximum Synchronous Offset MO5 MO4 MO3 MO2 0 0 ...
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Register: 0x07 General Purpose (GPREG) Read/Write write to this register will cause the data written to be output to the appropriate GPIO pin set to output mode in that function’s Purpose Pin Control (GPCNTL) ...
Page 153
... LSI53C1010 SCSI function is operating in the initiator mode, this register contains the first byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the first byte received is stored in this register, even if the present phase is the same as the last phase. The fi ...
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... I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the LSI53C1010 SCSI function starts executing normal SCSI SCRIPTS. REQ ACK BSY SEL ATN MSG C_D I_O Register: 0x0A SCSI Selector ID (SSID) Read Only ...
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... MDPE Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C1010 SCSI functions stack interrupts). SCSI Registers SEL ATN MSG ...
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... Master Parity Error Enable bit (bit 3 of (CTEST4)). Bus Fault This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the LSI53C1010 SCSI function is bus master, and is defined as a cycle that ends with a Bad Address or Target Abort Condition. Aborted This bit is set when an abort condition occurs ...
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... SCSI function is operating in single-step mode or automatically executing SCSI SCRIPTS. Any of the following conditions during instruction execution also sets this bit: The LSI53C1010 SCSI function is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring. A Block Move instruction is executed as an initiator ...
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Register: 0x0D SCSI Status Zero (SSTAT0) Read Only 7 ILF 0 ILF R OLF 4-42 Registers A Load and Store instruction is issued when the count value in the DMA Byte Counter (DBC) set ...
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... SCSI bus, and lost arbitration due to another SCSI device asserting the SSEL/ signal. WOA Won Arbitration When set, WOA indicates that the LSI53C1010 SCSI function has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode selected in the must be full arbitration and selection to set this bit ...
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Register: 0x0E SCSI Status One (SSTAT1) Read Only SDP0L MSG C_D I_O 4-44 Registers SDP0L Reserved Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/) corresponding to the ...
Page 161
... R Reserved LDSC Last Disconnect This bit is used in conjunction with the Connected (CON) bit in SCSI Control One detect the case in which a target device disconnects, and then a SCSI device selects or reselects the LSI53C1010 SCSI Registers SPL1 R LDSC 0 ...
Page 162
... ABRT 0 This is the only register that is accessible by the host CPU while a LSI53C1010 SCSI function is executing SCRIPTS (without interfering in the operation of the function used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts. ...
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... ABRT Abort Operation Setting this bit aborts the current operation under execution by the LSI53C1010 SCSI function. If this bit is set and an interrupt is received, clear this bit before reading the further aborted interrupts from being generated. The sequence to abort any operation is: 1. Set this bit. ...
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... Semaphore The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C1010 SCSI function is executing a SCRIPTS operation. This bit enables the SCSI function to notify an external processor of a predefined condition while SCRIPTS are running. The external processor may also notify the LSI53C1010 SCSI function of a predefi ...
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... After it has been set, this bit must be written to one to clear it. SIP SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C1010 SCSI function. The following conditions cause a SCSI interrupt to occur: A phase mismatch (initiator mode) or SATN/ becomes active (target mode) ...
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Register: 0x15 Interrupt Status One (ISTAT1) Read/Write FLSH SRUN SI 4-50 Registers A SCRIPTS instruction is executed in the single-step mode A SCRIPTS interrupt instruction is executed An illegal instruction is detected To determine exactly which condition(s) ...
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Register: 0x16 Mailbox Zero (MBOX0) Read/Write MBOX0 Mailbox Zero These are general purpose bits that may be read or written while SCRIPTS are running. They also may be read or written by the SCRIPTS processor. Note: ...
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Register: 0x18 Chip Test Zero (CTEST0) Read/Write 7 1 FMT Register: 0x19 Chip Test One (CTEST1) Read Only 7 0 FFL 4-52 Registers FMT Byte Empty in DMA FIFO These bits identify the lower bytes in ...
Page 169
Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write SIGP CIO Reserved SIGP Signal Process This bit is a copy of the SIGP bit in the Zero (ISTAT0) signal a ...
Page 170
... When this bit is set, data residing in the DMA FIFO is transferred to memory, starting at the address in the Next Address (DNAD) register. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C1010 SCSI function. Polling of FIFO flags is allowed during flush operations. and Base RAM). This is ...
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... Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C1010 SCSI function is executing SCRIPTS. During any Memory-to-Memory Moves operation, the contents of this register are preserved. The power-up value of this register is indeterminate. ...
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... A parity error during a bus master read is detected by the LSI53C1010 SCSI function. A parity error during a bus master write is detected by the target, and the LSI53C1010 SCSI function is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C1010 SCSI function does not interrupt if a master parity error occurs ...
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FBL3 FBL2 These bits steer the contents of the (CTEST6) register to the appropriate byte lane of the 64-bit DMA FIFO. If the FBL3 bit is set, then FBL2 through ...
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R BL2 R Register: 0x23 Chip Test Six (CTEST6) Read/Write 4-58 Registers Reserved Burst Length Bit 2 This bit works with bits 6 and 7 (BL[1:0]) in the Mode (DMODE) register to determine the burst length. For ...
Page 175
... Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the LSI53C1010 SCSI function is not in the target mode, Command phase. The DMA Byte Counter (DBC) hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during Table Indirect I/O SCRIPTS ...
Page 176
... DNAD 4-60 Registers DCMD DMA Command This 8-bit register determines the instruction for the LSI53C1010 SCSI function to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set.” DNAD ...
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Registers: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write DSP Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS SCSI ...
Page 178
... This value is also independent of the width (64-bit or 32-bit) of the data transfer on the PCI bus. The LSI53C1010 SCSI function asserts the Bus Request (PCIREQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data ...
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... Command. If this bit is set, then the destination address is in I/O space; if cleared, the destination address is in memory space. This function is useful for memory-to-register operations using the Memory Move instruction when a LSI53C1010 SCSI function is I/O mapped. Bits 4 and 5 of the Test Two (CTEST2) configuration status of the LSI53C1010 SCSI function. ...
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... Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the LSI53C1010 SCSI function to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a Memory-to- Memory Moves type, the third Dword is accessed in a subsequent bus ownership ...
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Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE This register contains the interrupt mask bits corresponding to the interrupting conditions described in the interrupt is masked by clearing the appropriate mask bit. ...
Page 182
... IRQM Cache Line Size Enable Setting this bit enables the LSI53C1010 SCSI function to sense and react to cache line boundaries set up by the DMA Mode (DMODE) or PCI register, whichever contains the smaller value. Clearing this bit disables the cache line size logic. ...
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... PCI bus. Prefetches of SCRIPTS instructions are 32-bits in width. SSM Single-Step Mode Setting this bit causes the LSI53C1010 SCSI function to stop after executing each SCRIPTS instruction and to generate a single step interrupt. When this bit is cleared the LSI53C1010 SCSI function does not stop after each instruction ...
Page 184
... R COM 4-68 Registers SCRIPTS Pointer (DSP) register when this bit is set. This bit is required if the LSI53C1010 SCSI function is in one of the following modes: Manual start mode – Bit 0 in the (DMODE) register is set Single-step mode – Bit 4 in the register is set When the LSI53C1010 SCSI function is executing ...
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Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER Register: 0x40 SCSI Interrupt Enable Zero (SIEN0) Read/Write 7 M/A 0 This register contains the interrupt mask bits corresponding to ...
Page 186
... Enable Response to Selection bit in the SCSI Chip ID (SCID) register. Reselected When set, this bit indicates the LSI53C1010 SCSI function is reselected by a SCSI target device. For this to occur, set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register. ...
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... This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse. PAR SCSI Parity/CRC/AIP Error This bit indicates the LSI53C1010 SCSI function detected a Parity/CRC/AIP error while receiving or sending SCSI data. See the Disable Halt on Parity/CRC/AIP error or SATN/ Condition bits in the SCNTL1 register for more information about when this condition is raised ...
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... An interrupt is masked by clearing the appropriate mask Reserved SCSI Bus Mode Change Setting this bit allows the LSI53C1010 to generate an interrupt when the DIFFSENS pin detects a change in voltage level that indicates the SCSI bus has changed between SE, LVD, or HVD modes. For example, when ...
Page 189
... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending; the LSI53C1010 SCSI functions stack interrupts. SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero (SIEN0) ...
Page 190
... Function Complete This bit is set when an arbitration only or full arbitration sequence is completed. Selected This bit is set when the LSI53C1010 SCSI function is selected by another SCSI device. For the LSI53C1010 SCSI function to respond to selection attempts, the Enable Response to Selection bit must be set in the Chip ID (SCID) register ...
Page 191
... Shadowed SGE Register (ShSGE) bit, in the Two (CCNTL2) UDC Unexpected Disconnect This bit is set when the LSI53C1010 SCSI function is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C1010 SCSI function operates in the initiator mode ...
Page 192
... SE, LVD, or HVD modes. Reserved Selection or Reselection Time-Out This bit is set when the SCSI device which the LSI53C1010 SCSI function is attempting to select or reselect does not respond within the programmed time-out period. See the description of the Zero (STIME0) register, bits [3:0], for more information on the time-out timer ...
Page 193
GEN General Purpose Timer Expired This bit is set when the general purpose timer expires. The time measured is the time between enabling and disabling of the timer. See the description of the Timer One (STIME1) information on the general ...
Page 194
Register: 0x46 Reserved 7 x This register is reserved. Register: 0x47 General Purpose Pin Control (GPCNTL) Read/Write This register is used to determine if the pins controlled by the Purpose (GPREG) correspond to bits [4:0] in the ...
Page 195
GPIO[4:2] GPIO Enable The general purpose control corresponds to bits [4:2] in the General Purpose (GPREG) GPIO4–GPIO2 pins. GPIO4 powers- general purpose output. GPIO[3:2] power-up as general purpose inputs. GPIO[1:0] GPIO Enable These bits are set at power-up ...
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SEL[3:0] Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA 4-80 Registers HTH [3:0], SEL [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selection Time-Out These bits select ...
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GENSF General Purpose Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16. Refer to the description for details. HTH [3:0], SEL [3:0], GEN [3:0] HTHSF Handshake-to-Handshake Timer Scale Factor Setting this bit causes ...
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Register: 0x4A Response ID Zero (RESPID0) Read/Write 7 x RESPID0 Register: 0x4B Response ID One (RESPID1) Read/Write 7 x RESPID1 4-82 Registers RESPID0 Response ID Zero Response ID Zero (RESPID0) (RESPID1) contain the selection or reselection ...
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... ID One (RESPID1) IDs on the bus. SLT Selection Response Logic Test This bit is set when the LSI53C1010 SCSI function is ready to be selected or reselected. This does not take into account the bus settle delay of 400 ns. This bit is used for functional test and fault purposes. ...
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... SCSI operations. When this bit is set and if the LSI53C1010 is functioning as an initiator, the device is waiting for the target to request data transfers. When this bit is set and if the LSI53C1010 is functioning as a target, then the initiator has sent the offset number of acknowledges. SCSI Synchronous Offset Maximum This bit indicates that the current synchronous SREQ/, SACK/ offset is the maximum specifi ...