21050-AA Intel Corporation, 21050-AA Datasheet
21050-AA
Specifications of 21050-AA
Related parts for 21050-AA
21050-AA Summary of contents
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... Programmable rotating arbitration function supporting up to six secondary bus masters — Secondary PCI bus parking at the 21050 Provides pins for buffer empty status and write posting control Supports perr and serr signals with error checking functionality ...
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... The 21050 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Manual Organization ............................................................................................ 1 1.4 General Description.............................................................................................. 2 1.5 Architecture Overview .......................................................................................... 4 2.0 21050 Pin Assignment ...................................................................................................... 5 2.1 Signal Types......................................................................................................... 6 2.2 Alphabetic 21050 Pin Assignment List ................................................................. 6 2.3 Numeric 21050 Pin Assignment List .................................................................... 9 3.0 Signal Description ........................................................................................................... 13 3.1 Primary PCI Bus Signals .................................................................................... 14 3.2 Secondary PCI Bus Signals ............................................................................... 15 3.3 Secondary Bus Arbiter Signals........................................................................... 17 3.4 Clock, Reset, and Miscellaneous Signals .......................................................... 17 4.0 Functional Description..................................................................................................... 19 4 ...
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... Non-Posted Write Operations ............................................................... 55 4.10 Data Synchronization ......................................................................................... 56 4.11 Exclusive Access ............................................................................................... 56 4.11.1 Acquiring Exclusive Access................................................................... 56 4.11.2 Maintaining Exclusive Access ............................................................... 59 4.11.3 Ending Exclusive Access ...................................................................... 60 4.11.4 21050 as a Locked Target .................................................................... 61 4.12 Error Handling .................................................................................................... 62 4.12.1 Address Parity Errors ............................................................................ 62 4.12.2 Data Parity Errors on Initiator Bus......................................................... 62 4.12.3 Data Parity Errors on Target Bus .......................................................... 63 4.12.4 Other Errors .......................................................................................... 64 4.13 PCI Bus Arbitration............................................................................................. 65 4.13.1 Primary PCI Bus Arbitration .................................................................. 65 4 ...
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... Electrical Specifications...................................................................................... 89 7.3 Interface Signal AC Electrical Specifications...................................................... 89 7.3.1 Interface Signal AC Timing Specifications ............................................ 90 7.3.2 Input Signal AC Timing Specifications .................................................. 91 Figures 1-1 21050 PCI-to-PCI Bridge on the System Board ................................................... 2 1-2 21050 PCI-to-PCI Bridge with Option Cards ........................................................ 3 1-3 21050 PCI-to-PCI Bridge Block Diagram ............................................................. 4 2-1 21050 Pinout Diagram.......................................................................................... 5 4-1 21050 Data Path ................................................................................................ 23 ...
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... Configuration Space Map................................................................................... 71 7-1 Package Dimensions ......................................................................................... 88 7-2 p_clk and s_clk AC Timing................................................................................. 91 7-3 AC Timing Waveforms ....................................................................................... 92 Tables 1-1 Major Sub-Blocks of the 21050 ............................................................................ 4 2-2 Alphabetic Pin Assignment List (Sheet ..................................................... 6 2-3 Numeric Pin Assignment List (Sheet ........................................................ 9 3-4 Signal Types ...................................................................................................... 13 3-5 Primary OCI Bus Signals (Sheet 1 of 2)............................................................. 14 3-6 Secondary PCI Bus Signals (Sheet ........................................................ 15 3-7 Secondary Bus Arbiter Signals ...
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... Primary Write Attempt Counter Register ............................................................ 82 5-16 Reserved Registers (50h – FFh) ........................................................................ 83 7-1 Lead Counts and Dimensional Attributes .......................................................... 87 7-2 Absolute Maximum Ratings................................................................................ 88 7-3 Functional Operating Range .............................................................................. 89 7-4 DC Specifications .............................................................................................. 89 7-5 Shared Signal Output Parameters ..................................................................... 89 7-6 p_clk and s_clk AC Timing ................................................................................. 90 7-7 Input Signal AC Timings..................................................................................... 91 7-8 xrst_l Timing Specifications................................................................................ 92 Preliminary Datasheet 21050 PCI-to-PCI Bridge vii ...
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... This data sheet describes the 21050 PCI-to-PCI bridge chip (21050). The 21050 expands the electrical capacity of all PCI systems. The 21050 allows motherboard designers to add more PCI devices or more PCI option card slots than a single PCI bus can support. Option card designers can use the 21050 to implement multiple device PCI option cards ...
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... PCI bus from devices on other PCI buses. This is a major benefit to system performance in some applications such as multimedia. The 21050 can extend a system beyond the electrical loading limits of a single PCI bus. Each new PCI bus created by the addition of a 21050 provides support for additional electrical loads. ...
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... Option card designers can use a 21050 to implement multiple device PCI option cards. Without a 21050, you can attach only one PCI device to the PCI option connector (the PCI Local Bus Specification, Revision 2.1 restricts PCI option cards to a single connection per PCI signal in the option card connector) ...
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... Machine and control logic for all transactions initiated on the primary interface, whether the PSM transaction is intended for the 21050 itself or a target on the secondary side of the 21050. Machine and control logic for all transactions initiated on the secondary interface. All such SPM transactions are intended for a target on the primary interface, since 21050 registers are not accessible from the secondary interface ...
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... Secondary PCI bus interface that interacts with the bus that is farther from the CPU • Power supply and miscellaneous functions Figure 2-1 shows the 21050 signals, and the 21050 pin assignments are listed in alphabetic and numeric order at the end of this chapter. Figure 2-1. 21050 Pinout Diagram ...
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... PCI-to-PCI Bridge 2.1 Signal Types The following table defines the 21050 signal types referred to in this chapter. Signal Type sts od P 2.2 Alphabetic 21050 Pin Assignment List Table 2-2 lists the 21050 pins in alphabetic order. Table 2-2. Alphabetic Pin Assignment List (Sheet ...
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... I s_ad<28> s_ad<29> 38 sts s_ad<30> 40 sts s_ad<31> s_bufne_l 91 sts s_cbe_l<0> 195 ts s_cbe_l<1> 208 I s_cbe_l<2> s_cbe_l<3> 29 21050 PCI-to-PCI Bridge Type sts sts ...
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... PCI-to-PCI Bridge Table 2-2. Alphabetic Pin Assignment List (Sheet Pin Pin Number s_cfn_l 52 s_clk 63 s_clk_o<0> 68 s_clk_o<1> 70 s_clk_o<2> 72 s_clk_o<3> 74 s_clk_o<4> 76 s_clk_o<5> 78 s_clk_o<6> 80 s_devsel_l 9 s_dispst_l 90 s_frame_l 13 s_gnt_l<5> 44 s_gnt_l<4> 45 s_gnt_l<3> 47 s_gnt_l<2> 48 s_gnt_l<1> 49 s_gnt_l<0> 51 s_irdy_l 12 s_lock_l 6 s_par 2 s_perr_l 5 s_req_l<0> 53 s_req_l<1> 54 s_req_l<2> 55 s_req_l<3> ...
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... Numeric 21050 Pin Assignment List Table 2-3 lists the 21050 pins in numeric order. Table 2-3. Numeric Pin Assignment List (Sheet Pin Pin Number nc 1 s_par 2 vdd 3 s_serr_l 4 ...
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... PCI-to-PCI Bridge Table 2-3. Numeric Pin Assignment List (Sheet Pin Pin Number vss 23 s_gnt_l<3> 47 s_gnt_l<2> 48 s_gnt_l<1> 49 vss 50 s_gnt_l<0> 51 s_cfn_l 52 s_req_l<0> 53 s_req_l<1> 54 s_req_l<2> 55 s_req_l<3> 56 s_req_l<4> 57 s_req_l<5> 58 vss 59 s_rst_l 60 vdd 61 vdd 62 s_clk vss 67 s_clk_o<0> 68 vdd 69 s_clk_o<1> 70 vss 71 s_clk_o< ...
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... P s_ad<04> 188 ts nc 189 -- s_ad<05> 190 ts vss 191 ts s_ad<06> 192 P s_ad<07> 193 ts vdd 194 ts s_cbe_l<0> 195 P vss 196 ts s_ad<08> 197 21050 PCI-to-PCI Bridge Type sts sts sts P sts sts P sts P sts ...
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... PCI-to-PCI Bridge Table 2-3. Numeric Pin Assignment List (Sheet Pin Pin Number nc 174 vss 199 s_ad<10> 200 1. nc—Do not connect these pins on the board Type Pin Pin Number -- s_ad<09> 198 P s_ad<11> 201 ts s_ad<12> 202 Type ts ts ...
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... Signal Description This chapter contains a detailed description of 21050 signals. Signals are divided into four major functions: • Primary PCI bus • Secondary PCI bus • Secondary bus arbiter • Clocks, reset, and miscellaneous Note: The _l symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal low-voltage level ...
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... PCI-to-PCI Bridge 3.1 Primary PCI Bus Signals The following table describes the primary PCI bus signals. Table 3-5. Primary OCI Bus Signals (Sheet Signal Name p_ad<31:0> p_cbe_l<3:0> p_frame_l p_trdy_l p_irdy_l p_stop_l p_lock_l p_idsel p_devsel_l 14 Type Description Primary PCI interface address/data. These signals represent a multiplexed PCI address and data bus ...
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... PCI bus. The assertion of s_frame_l indicates the beginning of sts an access. While s_frame_l is asserted, data transfers continue. The deassertion of s_frame_l indicates the final data phase. The bridge samples s_frame_l as an input and also drives s_frame_l when acting as the initiator of a transaction on the secondary PCI bus. 21050 PCI-to-PCI Bridge 15 ...
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... PCI-to-PCI Bridge Table 3-6. Secondary PCI Bus Signals (Sheet Signal Name s_trdy_l s_irdy_l s_stop_l s_lock_l s_devsel_l s_par s_serr_l s_perr_l 16 Type Description Secondary PCI interface target ready. This signal indicates the target agent’s ability to complete the current data phase of a transaction on the sts secondary PCI bus ...
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... Primary PCI bus reset. Forces the bridge to a known state. All register state is cleared and all primary PCI bus outputs are tristated. The p_rst_l I signal may be asynchronous with p_clk. The p_rst_l signal must be asserted for at least ten PCI clock cycles in order to reset the bridge properly. 21050 PCI-to-PCI Bridge 17 ...
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... O clock outputs must be used as a bridge s_clk input. The s_clk_o<6:0> clock may not be used to drive connector slots, and may not be used for the p_clk input of another 21050. Secondary PCI bus reset. Asserted by the bridge under any of the following conditions: • The p_rst_l signal is asserted. ...
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... Latency control, exclusive access, and error handling 4.1 PCI Bus Interfaces The 21050 bridges system traffic between the primary PCI bus or the PCI bus closer to the CPU, and the secondary PCI bus or the bus farther from the CPU. 4.2 Primary PCI Bus Interface The 21050 can act as either initiator or target on the primary PCI bus ...
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... The second address phase contains the most-significant 32 bits of the address on xad<31:0> and the transaction type command on xcbe_l<3:0>. The 21050 responds to all dual-address transactions on the secondary bus, and forwards them to the primary bus. The 21050 ignores all dual-address transactions initiated on the primary bus. ...
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... FFFFFFFFh. The Received Master Abort bit is set in the status register corresponding to the target bus. If the Master Abort Mode bit is set, then the 21050 is enabled to perform a target abort on the initiator bus when a master abort is detected on the target bus for read and non-posted write operations ...
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... PCI-to-PCI Bridge 4.5.1 Transaction Support Table 4-2 shows which transactions are supported by the 21050, and whether posting or prefetching is used for a particular transaction under normal operating conditions indicates transactions in which the initiator resides on the primary side and the target resides on the secondary side. ...
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... After data is successfully transferred to the target by assertion of yirdy_l and ytrdy_l, the 21050 transfers the write data from the initiator by asserting xtrdy_l ...
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... PCI-to-PCI Bridge Figure 4-2 shows a non-posted I/O write transaction where the bridge returns a target disconnect after the first data transfer. Figure 4-2. I/O Write Timing p_clk p_ad<31:0> p_cbe_l<3:0> p_frame_l p_irdy_l p_stop_l p_trdy_l p_devsel_l s_clk s_ad<31:0> s_cbe_l<3:0> s_frame_l s_irdy_l s_trdy_l s_devsel_l 4.5.3.2 Use of Non-Posted Write Transactions Non-posted write transactions are used for: • ...
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... For posted write transactions crossing the 21050, the initiator can post dwords of data to the 21050 while access to the target bus is acquired. If the 21050 does not receive a target response (an asserted value of xtrdy_l) by the time the eighth dword is about to be transferred, the 21050 performs a target disconnect on the eighth dword transfer ...
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... Memory write transactions • Memory write and invalidate transactions For posted write transactions, s_dispst_l must be deasserted or the Disable Posting bit must not be set in the Chip Control register in 21050 configuration space. In addition, the target bus must not be locked, that is, ylock_l must be deasserted. 26 p_clk p_ad< ...
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... Cache line size register is set to a value greater than the burst limit counter, and the burst limit counter is non-zero. The 21050 assumes that the cache line size is a power value that is not a power written into the cache line size register, the 21050 assumes the next lower power of 2 number as the cache line size (that is written, a cache line size used) ...
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... The 21050 holds the initiator in wait states with a target stall until the target device has returned ydevsel_l and ytrdy_l to the 21050, indicating that read data is ready. The 21050 propagates the read data across the 21050, asserting xtrdy_l to transfer it to the initiator ...
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... When the 21050 gains access to the target bus and begins the read transaction, it asserts all byte enables for all data transfers, regardless of which byte enables are asserted by the initiator. ...
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... In the case of xframe_l deassertion four extra dwords that are not requested by the initiator due to 21050 latency, may be read from the target. These extra dwords are discarded read boundary is encountered before the initiator deasserts xframe_l, no nonrequested dwords are read. ...
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... The 21050 imposes read boundaries on prefetchable reads. When a read boundary is reached, the 21050 deasserts yframe_l to the target at the beginning of the last data phase to indicate that only one more dword will be read. When the 21050 delivers this last longword to the initiator, the 21050 asserts xstop_l with xtrdy_l, causing a disconnect to occur on that data phase ...
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... Prefetch Disable bit is not set in the Chip Control register for upstream reads The 21050 assumes that the cache line size is a power value that is not a power written into the cache line size register, the 21050 assumes the next lower power of 2 number as the cache line size ( written, then a cache line size used) ...
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... Type 1 write (on the secondary PCI bus) to special cycle (on the primary PCI bus) Configuration write transactions cannot be posted. Transactions are disconnected after transfer of the first dword. The initiator is held in wait states by the 21050 until data is successfully transferred to the target. Configuration read transactions do not use prefetching. Transactions are disconnected after transfer of the first dword, and no additional dwords are read from the target during the transaction ...
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... Type 1 to Type 0 Conversion The 21050 forwards a Type 1 transaction downstream and converts Type 0 transaction when the transaction is intended for a device on the secondary PCI bus. A Type 1 transaction is forwarded downstream and converted to a Type 0 transaction when the following conditions are met during the address phase: • ...
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... The 21050 can generate Type 0 configuration cycles for devices. Configuration transactions with device numbers greater than 0Fh can still be forwarded, but the 21050 will not assert any of the s_ad<31:16> lines acting as secondary bus idsel lines. Such a transaction is likely to result in a master abort, unless some external assertion of a secondary bus idsel line is performed ...
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... Type 1 to Type 0 Configuration Write and Read 4.5.5.4 Type 1 to Type 1 Forwarding When the 21050 receives a Type 1 transaction that is intended for any device not on the secondary bus, it forwards the transaction as Type 1. Type 1 to Type 1 transactions may be forwarded upstream or downstream. In this case, the address is forwarded exactly as received on the initiating bus ...
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... Type 1 configuration transactions can be converted and forwarded as special cycles in either direction. The write data is used as the special cycle message. The 21050 forwards a Type 1 configuration write from the primary bus and converts special cycle on the secondary bus when the following conditions are met during the address phase: • ...
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... The value on s_ad<23:16> is equal to the 21050 primary bus number. If these conditions are met, the 21050 generates a special cycle on the primary bus using the same address and data used for the primary configuration write. 4.5.6 Special Cycles The 21050 ignores all special cycle transactions generated on either primary or secondary PCI buses. ...
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... Target If the 21050 is acting as a target during a transaction, then the only type of initiator termination possible is normal termination, in which the initiator deasserts xframe_l to indicate that the next data transfer is the last transfer, and then deasserts xirdy_l at the completion of the last data transfer. ...
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... The 21050 has two modes of responding to the initiator on the initiating PCI bus (where the 21050 is a target) when a master abort occurs on the target bus (where the 21050 is an initiator). The master abort response mode is set through the Master Abort Mode bit in the Bridge Control register. If the bit is not set (default mode), then the 21050 responds to a master abort as follows: • ...
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... Target Termination Initiated by Target If the 21050 acts as initiator and detects a target abort, retry, or disconnect through assertion of ystop_l, then the 21050 terminates the transaction on the target bus as soon as possible by deasserting yframe_l and asserting yirdy_l. The 21050 then deasserts yirdy_l one cycle later. ...
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... PCI-to-PCI Bridge Figure 4-11. I/O Write with Target Abort p_ad<31:0> p_cbe_l<3:0> p_frame_l p_irdy_l p_stop_l p_trdy_l p_devsel_l s_ad<31:0> s_cbe_l<3:0> s_frame_l s_irdy_l s_stop_l s_trdy_l s_devsel_l 42 p_clk Addr 3 s_clk Addr 3 Data 0 Data 0 LJ-03306.AI4 Preliminary Datasheet ...
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... If a target retry is detected on the target bus, the 21050 does the following: • If the transaction is a read or non-posted write, returns a target retry to the initiator. No data is transferred to or from the initiator or target. • If the transaction is a posted write, allows maximum of eight dwords to be transferred from the initiator to 21050 write buffers before returning a target disconnect ...
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... PCI-to-PCI Bridge Figure 4-13 shows a target retry during an I/O write, and target retry. Figure 4-13. Non-Posted I/O Write with Target Retry p_ad<31:0> p_cbe_l<3:0> p_frame_l p_irdy_l p_stop_l p_trdy_l p_devsel_l s_ad<31:0> s_cbe_l<3:0> s_frame_l s_irdy_l s_stop_l s_trdy_l s_devsel_l 44 p_clk Addr Data 1 3 s_clk Addr Data 1 3 Figure 4-14 ...
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... If the transaction is a posted write, then the 21050 allows maximum of 8 dwords to be transferred from the initiator to 21050 write buffers before returning a target disconnect (until the write buffer fills). ...
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... If a target retry or target disconnect is received by the 21050 during a posted write, the 21050 allows the initiator to continue posting write data until the write buffer is full (a maximum of 8 dwords). After the target retry or disconnect is received by the 21050, posted write data may still remain in the write buffers that has not been transferred to the target. ...
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... If the maximum number of attempts are made and the 21050 has not successfully transferred the buffered data, the 21050 asserts the p_serr_l line, if the p_serr_l driver enable is set and the serr Disable for Delivery of Posted Write Data Failed is not set. The write data is discarded. ...
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... Cache line or 256-dword boundary for memory-type reads, depending on various conditions • Burst count limit is reached A target abort is returned to the initiator by the 21050 only when a target abort is detected on the target bus during a read or non-posted write initiator abort occurs on the target bus and the Master Abort Mode bit is set. ...
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... If the address is outside of these ranges, the transaction is forwarded to the primary bus and the 21050 acts as an initiator on that bus, and as a target on the secondary bus. ...
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... Disabling the I/O Address Range If the I/O Limit Address register is set to a value less than the I/O Base Address register, the 21050 will not forward any I/O transactions from the primary to secondary bus, but will forward all I/O transactions initiated on the secondary bus to the primary bus. Note that the reset condition for the registers defines an address space of 0000h— ...
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... VGA Snoop Mode for snooping (forwarding) VGA palette I/O writes, enabled when the VGA Snoop bit is set in the Bridge Command register in configuration space 4.7.3.1 VGA Mode When VGA Mode is enabled, the 21050 forwards downstream all memory transactions that address frame buffer memory and all I/O transactions that address VGA I/O space (Section 4.7.1.3). ...
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... No extra stall cycles are added as a result of 21050 latency. Due to 21050 latency and prefetching four extra reads from the target may be performed at the end of a prefetched read transaction ...
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... If the target wait timer expires and the 21050 has the bus grant but cannot yet start the transaction because the target bus is still busy, no action occurs and the 21050 may continue with the transaction ...
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... For all read operations read is already initiated on one PCI bus intended for a target on the opposite PCI bus, and a second transaction, also intended to cross the 21050, is initiated on the opposite bus before the read occurs, the 21050 issues a retry to the initiator of the second transaction. 4.9.2 ...
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... Acquiring Exclusive Access If the initiator wants to create a lock on a target on the other side of the 21050, the initiator must first gain access to the xlock_l signal on its bus. A lock is gained on the initiating bus when the initiator: • ...
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... This implies that, if the intended target returns a target retry or target abort, causing the 21050 to relinquish the lock on the target bus, this target termination must be passed back to the initiator in order to force the initiator to relinquish the lock on the initiator bus. Because the first transaction of a locked series of transactions is a read, the 21050 normally performs this action ...
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... Figure 4-18 shows a target retry due to the target bus lock being busy. If the 21050 detects a master abort on the target bus, this condition is returned to the initiator bus as either normal termination or a target abort target abort is returned, the initiator relinquishes the lock. If normal termination occurs, then the initiator should recognize that the FFFFFFFFh read data condition indicates a master abort ...
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... The only effect this should have is to tie up the xlock_l signal longer than necessary. If the 21050 is configured to return target abort when a master abort is detected, both initiator and 21050 will relinquish the initiator and target bus locks ...
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... The xlock_l signal can be deasserted after this point, and should be deasserted as soon as possible. When exclusive access is terminated on the last data phase of a transfer, the 21050 may not be able to release the lock on the target bus until two cycles after the deassertion of xlock_l on the initiator bus ...
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... Error Handling The 21050 implements the data parity error signals p_perr_l and s_perr_l on both interfaces, and also implements the address parity and system error signals p_serr_l and s_serr_l on both interfaces. This section describes parity checking and generation, as well as the different conditions under which p_serr_l is asserted ...
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... Data Parity Errors on Target Bus If the 21050 detects a data parity error during a read operation on the target bus, then the 21050: • Sets the Detected Parity Error bit in the Status register that corresponds to the target bus. ...
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... The p_serr_l Driver Enable bit is set. • The serr disable for posted write parity errors is not set. In this case, the 21050 cannot pass back bad parity (because write) or assert xperr_l during the proper cycle (because data is posted). Table 4-4 lists parity error signaling for transactions that are forwarded. ...
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... The 21050 asserts p_req_l when it needs to forward a transaction upstream. During the cycle immediately after the 21050 detects an asserted level on p_gnt_l and the primary bus is idle, the 21050 starts the transaction on the primary bus by: • ...
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... If it deasserts one grant, it asserts the next grant no earlier than one PCI clock cycle later. If the 21050 detects that an initiator has failed to assert s_frame_l after 16 cycles of both grant assertion and an idle bus condition, the arbiter deasserts the grant. That initiator does not receive any more grants until it deasserts its request for at least one PCI clock cycle ...
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... Secondary Bus Parking If s_cfn_l is asserted low, the 21050 by default drives s_ad, s_cbe_l and s_par when the secondary bus is idle. If s_cfn_l is deasserted, the 21050 only drives these signals if s_req_l<0>, configured as the 21050 external grant, is asserted. Note: The s_cfn_l signal should be tied high or low through a resistive device since the input is connected to the diagnostic Nand tree and must be toggled during Nand tree testing ...
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... Primary Reset The 21050 has one reset input, p_rst_l. When asserted, p_rst_l causes the 21050 to immediately tristate all primary and secondary PCI interface signals. The 21050 resets all registers to 0 and clears all write buffers, unless designated otherwise deasserting edges may be asynchronous to p_clk and s_clk. ...
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... The 21050 can be reset by setting the Chip Reset bit in the Diagnostic Control register. As soon as the chip reset is completed, the Chip Reset bit is automatically cleared within six PCI clock cycles and the chip is ready for configuration. While the chip is in reset, the 21050 is inaccessible for any type of transaction to or across it. ...
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... Configuration Register Description This chapter provides programmer reference material for all 21050 configuration space registers. Configuration space registers include the predefined PCI device and 21050 registers, as well as other implementation-specific registers used during initialization. All registers located in configuration space are accessible only from the primary bus interface of the 21050. ...
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... PCI-to-PCI Bridge 5.1 Predefined Header Space Register Description This section provides a detailed description of predefined configuration space registers in the 21050. 5.1.1 Device ID and Vendor ID Register This section describes the device ID and vendor ID register Table 5-1. Device ID and Vendor ID Register Address 00 hex Access < ...
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... Sub-Class Code Prog. Interface — Read only. Base class code of the device. Reads as 06h to indicate that 21050 device. Sub-class code of the device. Reads as 04 hex to indicate that device is a 21050. Programming interface of the device. Reads as all 0’s. Revision ID for the 21050. ...
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... PCI-to-PCI Bridge 5.1.4 Primary Master Latency Timer/Cache Line Size/Header Type This section describes the primary master latency timer (MLT)/cache line size/header type register. 31 0Ch Reserved Table 5-4. Primary Master Latency Timer/Cache Line Size/Header Type Register Address 0C hex Access <31:24> <23:16> <15:11> ...
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... The subordinate bus number. Defines the inclusive upper limit of a range of bus numbers. This range determines whether configuration accesses are to be forwarded across the 21050 to the secondary bus. Reset to 0. The secondary bus number. Enables accesses to configuration space of a hierarchical PCI bus. If matched to a number driven during the Type 1 address cycle on the primary bus, the access is for a device on the secondary bus ...
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... Set to 01b to designate medium timing. Data Parity Detected. Set when the 21050 is acting as a master on the secondary bus, and s_perr_l is detected as asserted parity error is detected on secondary bus, and the Secondary Parity Response bit is set in the 21050 control register ...
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... The least-significant 4 bits are reserved and read only as 0. The 20 least-significant bits of the memory base address should be assumed to be 00000h. For memory read transactions, the 21050 does not prefetch data in this address range, and memory read transactions are limited to one data burst. This register is reset to 0. ...
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... The minimum memory <15:0> address range is 1 megabyte. The least-significant 4 bits are reserved and read only as 0. The 20 least significant bits of the memory base address should be assumed to be 00000h. The 21050 prefetches data in this address range. This register is reset to 0. Reserved : ...
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... Read/write. Read only. Reserved. Read only as 0. Fast back-to-back control. Reads only as zero to indicate that the 21050 will not perform fast back-to-back accesses to targets on the secondary bus. Secondary Bus Reset. When set high, the 21050 tristates secondary bus outputs and immediately terminates any transactions involving the secondary interface ...
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... PCI bus. This bit should be used for diagnostic purposes only. Reset to 0. s_perr_l diagnostic mode assertion control. When set to 1, the 21050 asserts the s_perr_l signal in response to all write data phases on the secondary bus intended for the 21050 or a primary bus device. This bit should be used for diagnostic purposes only. Reset Chip Control LJ-03251 ...
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... Reset to 0. Request mask timer. Designates the maximum value of the request mask timer, which is enabled after the 21050 issues a target retry to a master on the secondary bus. Reset to 0. 00b—mask timer not used 01b— ...
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... Reset to 0. Primary interface target wait timer. A programmable register which indicates the maximum number of PCI cycles that the 21050 waits to gain access to the target (secondary) bus for a transaction initiated on the primary bus. If the timer expires before the 21050 receives a grant for the secondary bus, the 21050 issues a target retry to the initiator on the primary bus and deasserts its secondary bus request ...
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... This section describes the reserved registers (50h-FFh). 31 50h : : : : : : : FFh Table 5-16. Reserved Registers (50h – FFh) Address 50h - FFh Access — Field description — Preliminary Datasheet Reserved : : : : : Reserved — Read only as 0. Reserved and read only as 0’s. 21050 PCI-to-PCI Bridge 00 LJ-03252.AI4 83 ...
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... The 21050 asserts p_perr_l in response to all write transaction data phases initiated on the primary bus and directed to or across the 21050 when the p_perr_l control bit is set. Similarly, when the s_perr_l control bit is set, the 21050 asserts s_perr_l in response to all write transaction data phases initiated on the secondary bus and directed across the 21050 chip ...
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... When set, all counters in excess of 8 bits are broken up into 4-bit chunks by a forced carry signal. The 4-bit chunks of any particular counter will count in parallel when the chip is in test mode. The test mode bit should not be set unless all 21050 state machines are idle, that is, there are no transactions in progress across the 21050 chip. ...
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... Specifications This chapter describes the mechanical and electrical specifications of the 21050. 7.1 Mechanical Specifications The following sections describe the mechanical specifications of the 21050. 7.1.1 21050 Package The 21050 PCI chip is packaged in a 208-pin PQFP. and Figure 7-1 shows the package dimensions of the 21050. ...
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... Absolute Maximum Ratings This section lists the absolute maximum ratings for the 21050. Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress ratings only. Operating beyond the functional operating range is not recommended and extended exposure beyond the functional operating range may affect reliability ...
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... Table 7-3. Functional Operating Range Parameter Operating ambient temperature, T Junction temperature, T Supply voltage V CC 7.2 Electrical Specifications Table 7-4 defines the dc parameters met by all 21050 signals under the conditions of the functional operating range. Table 7-4. DC Specifications Symbol Parameter V Input high voltage ih V Input low voltage ...
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... PCI-to-PCI Bridge Table 7-5. Shared Signal Output Parameters Symbol Parameter I Low clamp current cl Unloaded output rise t r time Unloaded output fall t f time See V/I curves in the PCI Specification. 1. –4 – 1.4)/0.024 2. out 11 – 5.25 out 78 4.4 – out – 0.015 5 ...
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... high 1 skew skew T cyc show the input signal ac timings. Minimum — 10 21050 PCI-to-PCI Bridge low low LJ-03253.AI4 Maximum Units — — ns — ns — ...
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... PCI-to-PCI Bridge Figure 7-3. AC Timing Waveforms Table 7-8 shows the timing specifications for xrst_l. Table 7-8. xrst_l Timing Specifications Symbol Parameter p_rst_l active time after power T prst stable p_rst_l active time after p_clk T prst–clk stable p_rst_l active to output float T prst–off ...
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Support, Products, and Documentation If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are ...