21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

CaseQFP  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 100/164:

Live Insertion

Download datasheet (812Kb)Embed
PrevNext
21150
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits are tied
high to disable their respective secondary clocks because those clocks are not connected to
anything. The next bit is tied low because that secondary clock output is connected to the 21150
s_clk input.
When the secondary reset signal, s_rst_l, is detected asserted and the primary reset signal, p_rst_l,
is detected deasserted, the 21150 drives gpio<2> low for one cycle to load the clock mask inputs
into the shift register. On the next cycle, the 21150 drives gpio<2> high to perform a shift
operation. This shifts the clock mask into msk_in; the most significant bit is shifted in first, and the
least significant bit is shifted in last.
Figure 20
shows a timing diagram for the load and for the beginning of the shift operation.
Figure 20. Clock Mask Load and Shift Timing
After the shift operation is complete, the 21150 tristates the gpio signals and can deassert s_rst_l if
the secondary reset bit is clear. The 21150 then ignores msk_in. Control of the gpio signal now
reverts to the 21150 gpio control registers. The clock disable mask can be modified subsequently
through a configuration write command to the secondary clock control register in device-specific
configuration space.
10.3

Live Insertion

The gpio<3> pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must be set to
1, and the output enable control for gpio<3> must be set to input only in the gpio output enable
control register.When live insertion mode is enabled, whenever gpio<3> is driven to a value of 1,
the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This
means that, as a target, the 21150 no longer accepts any I/O or memory transactions, on either
interface. When read, the register bits still reflect the value originally written by a configuration
write command; when gpio<3> is deasserted, the internal enable bits return to their original value
(as they appear when read from the command register). When this mode is enabled, as a master, the
21150 completes any posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because the 21150 is
not responding to any I/O or memory transactions during this time.
Note that the 21150 continues to accept configuration transactions in live insertion mode.
92
gpio<0>
gpio<2>
msk_in
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
LJ-04645.AI4
Preliminary
Datasheet