Figure 21. p_clk and s_clk Relative Timing
This chapter provides information about the 21150 clocks.
Primary and Secondary Clock Inputs
The 21150 implements a separate clock input for each PCI interface. The primary interface is
synchronized to the primary clock input, p_clk, and the secondary interface is synchronized to the
secondary clock input, s_clk.
The 21150 operates at a maximum frequency of 33 MHz, or 66 MHz if the 21150 is 66 MHz
capable. s_clk operates either at the same frequency or at half the frequency as p_clk.
The primary and secondary clock inputs must always maintain a synchronous relationship to each
other; that is, their edge relationships to each other are well defined. The maximum skew between
p_clk and s_clk rising edges is 7 ns, as is the maximum skew between p_clk and s_clk falling
edges. The minimum skew between p_clk and s_clk edges is 0 ns. The secondary clock edge must
never precede the primary clock edge.
primary and the secondary clock inputs.
Secondary Clock Outputs
The 21150 has 10 secondary clock outputs, s_clk_o<9:0>, that can be used as clock inputs for up to
nine external secondary bus devices and for the 21150 secondary clock input.
The s_clk_o outputs are derived from p_clk. The s_clk_o edges are delayed from p_clk edges by a
minimum of 0 ns and a maximum of 5 ns. The maximum skew between s_clk_o edges is 500 ps.
Therefore, to meet the p_clk and s_clk requirements stated in
delay is allowed for secondary clock etch returning to the device secondary clock inputs.
The rules for using secondary clocks are:
Each secondary clock output is limited to one load.
One of the secondary clock outputs must be used for the 21150 s_clk input.
illustrates the timing relationship between the
11.1, no more than 2 ns of