21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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21150
Dword Bit
0
I/O space enable
1
Memory space enable
2
Master enable
3
Special cycle enable
Memory write and
4
invalidate enable
5
VGA snoop enable
106
Name
R/W
Controls the 21150’s response to I/O
transactions on the primary interface.
When 0—The 21150 does not respond to I/O
transactions initiated on the primary bus.
R/W
\When 1—The 21150 response to I/O
transactions initiated on the secondary bus is
enabled.
Reset value: 0.
Controls the 21150’s response to memory
transactions on the 21150 primary interface.
When 0—The 21150 does not respond to
memory transactions initiated on the primary
bus.
R/W
When 1—The 21150 response to memory
transactions initiated on the primary bus is
enabled.
Reset value: 0.
Controls the 21150’s ability to initiate memory
and I/O transactions on the primary bus on
behalf of an initiator on the secondary bus.
Forwarding of configuration transactions is not
affected.
When 0—The 21150 does not respond to I/O
or memory transactions on the secondary
R/W
interface and does not initiate I/O or memory
transactions on the primary interface.
When 1—The 21150 is enabled to operate as
an initiator on the primary bus and responds to
I/O and memory transactions initiated on the
secondary bus.
Reset value: 0.
The 21150 ignores special cycle transactions,
R
so this bit is read only and returns 0.
The 21150 generates memory write and
invalidate transactions only when operating on
behalf of another master whose memory write
R
and invalidate transaction is crossing the
21150.
This bit is read only and returns 0.
Controls the 21150’s response to VGA-
compatible palette write transactions. VGA
palette write transactions correspond to I/O
transactions whose address bits are as follows:
• p_ad<9:0> are equal to 3C6h, 3C8h, and
3C9h.
• p_ad<15:10> are not decoded.
R/W
• p_ad<31:16> must be 0.
When 0—VGA palette write transactions on
the primary interface are ignored unless they
fall inside the 21150’s I/O address range.
When 1—VGA palette write transactions on
the primary interface are positively decoded
and forwarded to the secondary interface.
Reset value: 0.
Description
Preliminary
Datasheet