21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Dword Bit
6
Parity error response
7
Wait cycle control
8
SERR# enable
9
Fast back-to-back enable
15;10
Reserved
15.1.4
Primary Status Register—Offset 06h
This section describes the primary status register.
These bits affect the status of the 21150 primary interface. Bits reflecting the status of the
secondary interface are found in the secondary status register. W1TC indicates that writing 1 to a
bit sets that bit to 0. Writing 0 has no effect.
Dword address = 04h
Byte enable p_cbe_l<3:0> = 00xxb
Preliminary
Datasheet
Name
R/W
Controls the 21150’s response when a parity
error is detected on the primary interface.
When 0—The 21150 does not assert p_perr_l,
nor does it set the data parity reported bit in the
status register. The 21150 does not report
address parity errors by asserting p_serr_l.
R/W
When 1—The 21150 drives p_perr_l and
conditionally sets the data parity reported bit in
the status register when a data parity error is
detected (see
p_serr_l assertion when address parity errors
are detected on the primary interface.
Reset value: 0.
Reads as 0 to indicate that the 21150 does not
R
perform address or data stepping.
Controls the enable for p_serr_l on the primary
interface.
When 0—Signal p_serr_l cannot be driven by
the 21150.
R/W
When 1—Signal p_serr_l can be driven low by
the 21150 under the conditions described in
Section
Reset value: 0.
Controls the ability of the 21150 to generate
fast back-to-back transactions on the primary
bus.
When 0—The 21150 does not generate back-
R/W
to-back transactions on the primary bus.
When 1—The 21150 is enabled to generate
back-to-back transactions on the primary bus.
Reset value: 0.
R
Reserved. Returns 0 when read.
21150
Description
Section
7.0). The 21150 allows
7.4.
107