21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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21150
Dword Bit
23:16
Subordinate bus number
15.1.15
Secondary Latency Timer Register—Offset 1Bh
This section describes the secondary latency timer register.
Dword address = 18h
Byte enable p_cbe_l<3:0> = 0xxxb
Dword Bit
31:24
Secondary latency timer
15.1.16
I/O Base Address Register—Offset 1Ch
This section describes the I/O base address register.
This register must be initialized by configuration software.
Dword address = 1Ch
Byte enable p_cbe_l<3:0> = xxx0b
112
Name
R/W
Indicates the number of the highest numbered
PCI bus that is behind (or subordinate to) the
21150. Used in conjunction with the secondary
bus number to determine when to respond to
Type 1 configuration transactions on the
R/W
primary interface and pass them to the
secondary interface as a Type 1 configuration
transaction.
Reset value: 0.
Name
R/W
Master latency timer for the secondary
interface. Indicates the number of PCI clock
cycles from the assertion of s_frame_l to the
expiration of the timer when the 21150 is acting
as a master on the secondary interface. All bits
are writable, resulting in a granularity of one
PCI clock cycle.
R/W
When 0—The 21150 ends the transaction after
the first data transfer when the 21150’s
secondary bus grant has been deasserted,
with the exception of memory write and
invalidate transactions.
Reset value: 0.
Description
Description
Preliminary
Datasheet