21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Capability ID Register Offset DCh

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21150
Dword Bit
Secondary master
25
timeout
26
Master timeout status
Master timeout SERR#
27
enable
31:28
Reserved
15.1.32
Capability ID Register—Offset DCh
This section describes the capability ID register. (Implemented in the 21150-AB and later revisions
only. In the 21150-AA, these registers are reserved.)
Dword address = DCh
Byte enable p_cbe_l<3:0> = xxx0b
Dword Bit
7:0
CAP_ID
122
Name
R/W
Sets the maximum number of PCI clock cycles
that the 21150 waits for an initiator on the
secondary bus to repeat a delayed transaction
request. The counter starts once the delayed
transaction completion is at the head of the
queue. If the master has not repeated the
transaction at least once before the counter
expires, the 21150 discards the transaction
R/W
from its queues.
When 0—The primary master timeout value is
15
2
PCI clock cycles, or 0.983 ms for a 33-MHz
bus.
When 1—The value is 2
30.7 s for a 33-MHz bus.
Reset value: 0.
This bit is set to 1 when either the primary
master timeout counter or the secondary
master timeout counter expires and a delayed
R/W1TC
transaction is discarded from the 21150’s
queues. Write 1 to clear.
Reset value: 0.
Controls assertion of p_serr_ during a master
timeout.
When 0—Signal p_serr_l is not asserted as a
result of a master timeout.
When 1—Signal p_serr_l is asserted when
R/W
either the primary master timeout counter or
the secondary master timeout counter expires
and a delayed transaction is discarded from
the 21150’s queues. The SERR# enable bit in
the command register must also be set.
Reset value: 0.
R
Reserved. Returns 0 when read.
Name
R/W
Enhanced capabilities ID. Reads only as 01h to
R/W
indicate that these are power management
enhanced capability registers.
Description
10
PCI clock cycles, or
Description
Preliminary
Datasheet