21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 133/164:

Device-Specific Configuration Registers

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Dword Bit
23
BPCC_EN
15.1.37
Data Register—Offset E3h
This section describes the data register.
Dword address = E0h
Byte enable p_cbe_l<3:0> = 0xxxb
Dword Bit
31:24
Data
15.2

Device-Specific Configuration Registers

This section provides a detailed description of the 21150 device-specific configuration registers.
Each field has a separate description.
Fields that have the same configuration address are selectable by turning on (driving low) the
appropriate byte enable bits on p_cbe_l during the data phase. To select all fields of a configuration
address, drive all byte enable bits low.
All reserved fields and registers are read only and always return 0.
15.2.1
Chip Control Register—Offset 40h
This section describes the chip control register.
Dword address = 40h
Byte enable p_cbe_l<3:0> = xxx0b
Preliminary
Datasheet
Name
R/W
Bus Power/Clock Control Enable. When the
bpcce pin is tied high, this bit reads as a 1 to
indicate that the bus power/clock control
mechanism is enabled, as described in B2_B3
R
(bit 22). When the bpcce pin is tied low, this bit
reads as a 0 to indicate that the bus power/
clock control mechanism is disabled
(secondary clocks are not disabled when this
device is placed in D3
Name
R/W
Data register. This register is not implemented
R
and reads 00h.
21150
Description
.)
hot
Description
125