21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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21150
Dword Bit
0
Reserved
Memory write disconnect
1
control
3:2
Reserved
Secondary bus prefetch
4
disable
5
Live insertion mode
7:6
Reserved
15.2.2
Diagnostic Control Register—Offset 41h
This section describes the diagnostic control register.
W1TR indicates that writing 1 in this bit position causes a chip reset to occur. Writing 0 has no
effect.
Dword address = 40h
Byte enable p_cbe_l<3:0> = xx0xb
126
Name
R/W
R
Reserved. Returns 0 when read.
Controls when the 21150, as a target,
disconnects memory write transactions.
When 0—The 21150 disconnects on queue full
or on a 4KB boundary.
R/W
When 1—The 21150 disconnects on a cache
line boundary, as well as when the queue fills
or on a 4KB boundary.
Reset value: 0.
R
Reserved. Returns 0 when read.
Controls the 21150’s ability to prefetch during
upstream memory read transactions.
When 0—The 21150 prefetches and does not
forward byte enable bits during memory read
transactions.
When 1—The 21150 requests only one Dword
R/W
from the target during memory read
transactions and forwards read byte enable
bits. The 21150 returns a target disconnect to
the requesting master on the first data transfer.
Memory read line and memory read multiple
transactions are still prefetchable.
Reset value: 0.
Enables hardware control of transaction
forwarding in the 21150.
When 0—Pin gpio<3> has no effect on the I/O,
memory, and master enable bits.
When 1—If the output enable control for
gpio<3> is set to input only in the gpio output
R/W
enable control register, this bit enables
gpio<3> to mask the I/O enable, memory
enable, and master enable bits to 0. These
enable bits are masked when gpio<3> is driven
high. When this occurs, the 21150 stops
accepting I/O and memory transactions.
Reset value: 0.
R
Reserved. Returns 0 when read.
Description
Preliminary
Datasheet