21150-AB Intel Corporation, 21150-AB Datasheet - Page 138

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
21150
15.2.6
gpio Output Enable Control Register—Offset 66h
This section describes the gpio output enable control register.
Dword address = 64h
Byte enable p_cbe_l<3:0> = x0xxb
Dword Bit
GPIO output enable write-
19:16
1-to-clear
GPIO output enable write-
23:20
1-to-set
15.2.7
gpio Input Data Register—Offset 67h
This section describes the gpio input data register.
Dword address = 64h
Byte enable p_cbe_l<3:0> = 0xxxb
Dword Bit
27:24
Reserved
31:28
GPIO input
15.2.8
Secondary Clock Control Register—Offset 68h
This section describes the secondary clock control register.
Dword address = 68h
Byte enable p_cbe_l<3:0> = xx00b
130
Name
R/W
The gpio<3:0>output enable control write-1-to-
clear. Writing 1 to any of these bits configures
the corresponding gpio<3:0> pin as an input
only; that is, the output driver is tristated.
R/W1TC
Writing 0 to this register has no effect. When
read, reflects the last value written.
Reset value: 0 (all pins are input only).
The gpio<3:0> output enable control write-1-to-
set. Writing 1 to any of these bits configures
the corresponding gpio<3:0> pin as
bidirectional, that is, enables the output driver
and drives the value set in the output data
R/W1TS
register (65h). Writing 0 to this register has no
effect. When read, reflects the last value
written.
Reset value: 0 (all pins are input only).
Name
R/W
R
Reserved. Returns 0 when read.
This read-only register reads the state of the
gpio<3:0> pins. This state is updated on the
R
PCI clock cycle following a change in the gpio
pins.
Description
Description
Preliminary
Datasheet

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