21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Table 38. Boundary-Scan Order (Sheet 5 of 5)
Pin
Signal Name
Number
179
s_frame_l
180
s_cbe_l<2>
182
s_ad<16>
183
s_ad<17>
185
s_ad<18>
186
s_ad<19>
188
s_ad<20>
189
s_ad<21>
191
s_ad<22>
192
s_ad<23>
194
s_cbe_l<3>
195
s_ad<24>
197
s_ad<25>
198
s_ad<26>
200
s_ad<27>
201
s_ad<28>
203
s_ad<29>
204
s_ad<30>
206
s_ad<31>
207
s_req_l<0>
16.7
Initialization
The test access port controller and the instruction register output latches are initialized when the
trst_l input is asserted. The test access port controller enters the test-logic reset state. The
instruction register is reset to hold the bypass register instruction. During test-logic reset state, all
JTAG test logic is disabled, and the chip performs normal functions. The test access port controller
leaves this state only when an appropriate JTAG test operation sequence is sent on the tms and tck
pins.
Preliminary
Datasheet
Boundary-Scan
Group Disable
Register Number
Number
29
7
30
6
31
6
32
6
33
6
34
6
35
6
36
6
37
6
38
6
39
6
40
6
41
6
42
6
43
6
44
6
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6
46
6
47
48
6
49
21150
Group Disable Cell
6
141