21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 153/164:

Clock Timing Specifications

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17.4.1

Clock Timing Specifications

The ac specifications consist of input requirements and output responses. The input requirements
consist of setup and hold times, pulse widths, and high and low times. Output responses are delays
from clock to signal. The ac specifications are defined separately for each clock domain within the
21150.
Figure 23
shows the ac parameter measurements for the p_clk and s_clk signals.
Table 43
specify p_clk and s_clk parameter values for clock signal ac timing. See also
for a further illustration of signal timing. Unless otherwise noted, all ac parameters are guaranteed
when tested within the functional operating range of
Figure 23. PCI Clock Signal AC Parameter Measurements
V
t2
V t3
p_clk
T
r
s_clk
Note:
_ 2.0 V for 5-V clocks; 0.5 V
V
t1
_ 1.5 V for 5-V clocks; 0.4 V
V
t2
_ 0.8 V for 5-V clocks; 0.3 V
V
t3
Table 42. 33 MHz PCI Clock Signal AC Parameters (Sheet 1 of 2)
Symbol
p_clk, s_clk
T
cyc
cycle time
p_clk, s_clk
T
high
high time
p_clk, s_clk low
T
low
time
p_clk, s_clk
slew rate
Delay from
T
sclk
p_clk to s_clk
p_clk rising to
T
sclkr
s_clk_o rising
Preliminary
Datasheet
Table
T
cyc
V
t1
T
high
T
f
T
r
V
t1
T
V
high
t2
V t3
T
T
skew
skew
T
cyc
for 3.3-V clocks
cc
for 3.3-V clocks
cc
for 3.3-V clocks
cc
Parameter
Minimum
Maximum
30
11
11
1
4
1
0
10
0
5
Table 42
and
Figure 24
40.
T
low
T
f
T
low
LJ-04738.AI4
Unit
ns
ns
ns
V/ns
ns
ns
21150
145