21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 155/164:

MHz PCI Signal Timing

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Figure 24. PCI Signal Timing Measurement Conditions
Table 44. 33 MHz PCI Signal Timing
Symbol
CLK to signal
valid delay—
T
val
bused
signals
CLK to signal
valid delay—
T
val(ptp)
point-to-
point
Float to active
T
on
delay
Active to float
T
off
delay
Input setup
T
time—bused
su
signals
Input setup
time to CLK—
T
su(ptp)
point-to-
point
Input signal
T
hold time from
h
CLK
1.
See
Figure
23.
2.
All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized
to s_clk.
3.
Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad,
p_cbe_l, p_par, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_lock_l, p_devsel_l, p_stop_l,
p_idsel, s_ad, s_cbe_l, s_par, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_lock_l, s_devsel_l, and
s_stop_l.
Preliminary
Datasheet
CLK
V
test
T
val
Output
Valid
T
on
Input
Valid
T
su
Note:
_ 1.5 V for 5-V signals; 0.4 V
V
test
Parameter
Minimum
Maximum
2
11
1,2,3
2
12
1,2,3
2
1,23
28
1,2
7
1,2,3
10, 12
1,2,3
0
1,2
21150
T
inval
T
off
T
h
for 3.3-V signals
cc
LJ-04739.AI4
Unit
ns
ns
ns
ns
ns
ns
ns
147