21150-AB Mhz Pci Signal Timing - Intel Corporation

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
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Preliminary
Figure 24. PCI Signal Timing Measurement Conditions
Table 44. 33 MHz PCI Signal Timing
Datasheet
1.
2.
3.
T
T
T
T
T
T
T
on
off
su
su(ptp)
val
val(ptp)
h
See
All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized
to s_clk.
Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad,
p_cbe_l, p_par, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_lock_l, p_devsel_l, p_stop_l,
p_idsel, s_ad, s_cbe_l, s_par, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_lock_l, s_devsel_l, and
s_stop_l.
Symbol
Figure
23.
CLK to signal
valid delay—
bused
signals
CLK to signal
valid delay—
point-to-
point
Float to active
delay
Active to float
delay
Input setup
time—bused
signals
Input setup
time to CLK—
point-to-
point
Input signal
hold time from
CLK
Parameter
1,2
1,2,3
1,2,3
1,23
1,2
Note:
Output
1,2,3
1,2,3
Input
CLK
V
test
_ 1.5 V for 5-V signals; 0.4 V
2
2
2
7
10, 12
0
Minimum
V
T
test
val
T
T
on
su
Valid
11
12
28
Valid
Maximum
cc
T
for 3.3-V signals
off
T
T
h
inval
LJ-04739.AI4
ns
ns
ns
ns
ns
ns
ns
Unit
21150
147

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