21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 156/164:

Reset Timing Specifications

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21150
Table 45. 66 MHz PCI Signal Timing
Symbol
CLK to signal
valid delay—
T
val
bused
signals
CLK to signal
valid delay—
T
val(ptp)
point-to-
point
Float to active
T
on
delay
Active to float
T
off
delay
Input setup
T
time—bused
su
signals
Input setup
time to CLK—
T
su(ptp)
point-to-
point
Input signal
T
hold time from
h
CLK
1.
See
Figure
23.
2.
All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized
to s_clk.
3.
Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad,
p_cbe_l, p_par, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_lock_l, p_devsel_l, p_stop_l,
p_idsel, s_ad, s_cbe_l, s_par, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_lock_l, s_devsel_l, and
s_stop_l.
17.4.3

Reset Timing Specifications

Table 46
shows the reset timing specifications for p_rst_l and s_rst_l.
.
Table 46. Reset Timing Specifications (Sheet 1 of 2)
Symbol
p_rst_l active
T
time after power
rst
stable
p_rst_l active
T
time after p_clk
rst-clk
stable
p_rst_l active-
T
to-output float
rst-off
delay
s_rst_l active
after p_rst_ll
Tsrst
assertion
148
Parameter
Minimum
Maximum
2
6
1,2,3
2
6
1,2,3
2
1,23
14
1,2
3
1,2,3
5
1,2,3
0
1,2
Parameter
Minimum
Maximum
1
100
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
s
s
ns
ns
Preliminary
Datasheet