21150-AB Intel Corporation, 21150-AB Datasheet - Page 20

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
21150
Table 5.
Secondary PCI Bus Interface Signals (Sheet 2 of 3)
Signal Name
s_irdy_l
s_trdy_l
s_devsel_l
s_stop_l
12
Type
Description
Secondary PCI interface IRDY#. Signal s_irdy_l is driven by
the initiator of a transaction to indicate the initiator’s ability to
complete the current data phase on the secondary PCI bus.
During a write transaction, assertion of s_irdy_l indicates that
valid write data is being driven on the s_ad bus. During a read
STS
transaction, assertion of s_irdy_l indicates that the initiator is
able to accept read data for the current data phase. Once
asserted during a given data phase, s_irdy_l is not deasserted
until the data phase completes. When the secondary bus is
idle, s_irdy_l is driven to a deasserted state for one cycle and
then is sustained by an external pull-up resistor.
Secondary PCI interface TRDY. Signal s_trdy_l is driven by
the target of a transaction to indicate the target’s ability to
complete the current data phase on the secondary PCI bus.
During a write transaction, assertion of s_trdy_l indicates that
the target is able to accept write data for the current data
phase. During a read transaction, assertion of s_trdy_l
STS
indicates that the target is driving valid read data on the s_ad
bus. Once asserted during a given data phase, s_trdy_l is not
deasserted until the data phase completes. When the
secondary bus is idle, s_trdy_l is driven to a deasserted state
for one cycle and then is sustained by an external pull-up
resistor.
Secondary PCI interface DEVSEL#. Signal s_devsel_l is
asserted by the target, indicating that the device is accepting
the transaction. As a target, the 21150 performs positive
decoding on the address of a transaction initiated on the
secondary bus in order to determine whether to assert
STS
s_devsel_l. As an initiator of a transaction on the secondary
bus, the 21150 looks for the assertion of s_devsel_l within five
cycles of s_frame_l assertion; otherwise, the 21150 terminates
the transaction with a master abort. When the secondary bus
is idle, s_devsel_l is driven to a deasserted state for one cycle
and then is sustained by an external pull-up resistor.
Secondary PCI interface STOP#. Signal s_stop_l is driven by
the target of the current transaction, indicating that the target is
requesting the initiator to stop the current transaction on the
secondary bus.
• When s_stop_l is asserted in conjunction with s_trdy_l
and s_devsel_l assertion, a disconnect with data transfer
is being signaled.
• When s_stop_l and s_devsel_l are asserted, but s_trdy_l
STS
is deasserted, a target disconnect without data transfer is
being signaled. When this occurs on the first data phase,
that is, no data is transferred during the transaction, this is
referred to as a target retry.
• When s_stop_l is asserted and s_devsel_l is deasserted,
the target is signaling a target abort.
When the secondary bus is idle, s_stop_l is driven to a
deasserted state for one cycle and then is sustained by an
external pull-up resistor.
Preliminary
Datasheet

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