21150-AB Miscellaneous Signals - Intel Corporation

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
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21150
2.7
16
Table 10. Miscellaneous Signals

Miscellaneous Signals

Table 10
msk_in
p_vio
s_vio
config66
p_m66ena
s_m66ena
Signal Name
describes the miscellaneous signals.
I
I
I
I
I
I/OD
Type
Secondary clock disable serial input. This input-only signal is
used by the hardware mechanism to disable secondary clock
outputs. The serial stream is received by msk_in, starting
when p_rst is detected deasserted and s_rst_l is detected
asserted. This serial data is used for selectively disabling
secondary clock outputs and is shifted into the secondary
clock control configuration register. This input can be tied low
to enable all secondary clock outputs, or tied high to drive all
secondary clock outputs high.
Primary interface I/O voltage. This signal must be tied to either
3.3 V or 5 V, corresponding to the signaling environment of the
primary PCI bus as described in the PCI Local Bus
Specification, Revision 2.1 . When any device on the primary
PCI bus uses 5-V signaling levels, tie p_vio to 5 V. Signal
p_vio is tied to 3.3 V only when all the devices on the primary
bus use 3.3-V signaling levels.
Secondary interface I/O voltage. This signal must be tied to
either 3.3 V or 5 V, corresponding to the signaling environment
of the secondary PCI bus as described in the PCI Local Bus
Specification, Revision 2.1 . When any device on the
secondary PCI bus uses 5-V signaling levels, tie s_vio to 5 V.
Signal s_vio is tied to 3.3 V only when all the devices on the
secondary bus use 3.3-V signaling levels.
Configure 66 MHz operation. This input only pin is used to
specify if the 21150 is capable of running at 66 MHz. If the pin
is tied high, then the device can be run at 66 MHz. If the pin is
tied low, then the 21150 can only function under the 33 MHz
PCI specification.
Primary interface 66 MHz enable. This input-only signal pin is
used to designate the primary interface bus speed. This signal
should be pulled low for 33 MHz operation on the primary bus.
In this case, the s_m66ena pin will be driven low, forcing the
secondary interface to also run at 33 MHz. For 66 MHz
operation on the primary bus, this signal should be pulled high.
Secondary interface 66 MHz enable. This signal pin is used to
designate the secondary interface bus speed. If the primary
bus is operating at 33 MHz (i.e. if p_m66ena is low), then the
s_m66ena pin will be driven low by the 21150 forcing the
secondary bus to operate at 33 MHz. If the primary bus is
operating at 66 MHz, then the s_m66ena pin is an input and
should be externally pulled high for the secondary bus to
operate at 66 MHz or low for the secondary bus to operate at
33 MHz.
Description
Preliminary
Datasheet

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