21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 38/164:

Posted Write Transactions

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21150
4.5.1

Posted Write Transactions

Posted write forwarding is used for memory write and for memory write and invalidate
transactions.
When the 21150 determines that a memory write transaction is to be forwarded across the bridge,
the 21150 asserts DEVSEL# with medium timing and TRDY# in the same cycle, provided that
enough buffer space is available in the posted data queue for the address and at least 8 Dwords of
data. This enables the 21150 to accept write data without obtaining access to the target bus. The
21150 can accept 1 Dword of write data every PCI clock cycle; that is, no target wait states are
inserted. This write data is stored in internal posted write buffers and is subsequently delivered to
the target.
The 21150 continues to accept write data until one of the following events occurs:
The initiator terminates the transaction by deasserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an aligned
4KB boundary, depending on the transaction type.
The posted write data buffer fills up.
When one of the last two events occurs, the 21150 returns a target disconnect to the requesting
initiator on this data phase to terminate the transaction. Once the posted write data moves to the
head of the posted data queue, the 21150 asserts its request on the target bus. This can occur while
the 21150 is still receiving data on the initiator bus. When the grant for the target bus is received
and the target bus is detected in the idle condition, the 21150 asserts FRAME# and drives the stored
write address out on the target bus. On the following cycle, the 21150 drives the first Dword of
write data and continues to transfer write data until all write data corresponding to that transaction
is delivered, or until a target termination is received. As long as write data exists in the queue, the
21150 can drive 1 Dword of write data each PCI clock cycle; that is, no master wait states are
inserted. If write data is flowing through the 21150 and the initiator stalls, the 21150 may have to
insert wait states on the target bus if the queue empties.
Figure 6
shows a memory write transaction in flow-through mode, where data is being removed
from buffers on the target interface while more data is being transferred into the buffers on the
master interface.
30
Preliminary
Datasheet