21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

CaseQFP  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 4/164

Download datasheet (812Kb)Embed
PrevNext
21150
4.8
Transaction Termination ..................................................................................... 47
4.8.1
Master Termination Initiated by the 21150 ............................................. 47
4.8.2
Master Abort Received by the 21150 ..................................................... 48
4.8.3
Target Termination Received by the 21150 ........................................... 50
4.8.3.1 Delayed Write Target Termination Response ........................... 50
4.8.3.2 Posted Write Target Termination Response ............................. 51
4.8.3.3 Delayed Read Target Termination Response ........................... 51
4.8.4
Target Termination Initiated by the 21150 ............................................. 53
4.8.4.1 Target Retry .............................................................................. 53
4.8.4.2 Target Disconnect ..................................................................... 54
4.8.4.3 Target Abort .............................................................................. 54
5.0
Address Decoding............................................................................................................ 55
5.1
Address Ranges.................................................................................................. 55
5.2
I/O Address Decoding ......................................................................................... 55
5.2.1
I/O Base and Limit Address Registers ................................................... 56
5.2.2
ISA Mode ............................................................................................... 57
5.3
Memory Address Decoding ................................................................................. 58
5.3.1
Memory-Mapped I/O Base and Limit Address Registers ....................... 59
5.3.2
Prefetchable Memory Base and Limit Address Registers ...................... 60
5.3.3
Prefetchable Memory 64-Bit Addressing Registers................................ 61
5.4
VGA Support ....................................................................................................... 62
5.4.1
VGA Mode.............................................................................................. 62
5.4.2
VGA Snoop Mode .................................................................................. 63
6.0
Transaction Ordering ....................................................................................................... 65
6.1
Transactions Governed by Ordering Rules ......................................................... 65
6.2
General Ordering Guidelines .............................................................................. 66
6.3
Ordering Rules .................................................................................................... 66
6.4
Data Synchronization .......................................................................................... 68
7.0
Error Handling .................................................................................................................. 69
7.1
Address Parity Errors .......................................................................................... 69
7.2
Data Parity Errors................................................................................................ 70
7.2.1
Configuration Write Transactions to 21150 Configuration Space .......... 70
7.2.2
Read Transactions ................................................................................. 70
7.2.3
Delayed Write Transactions ................................................................... 71
7.2.4
Posted Write Transactions ..................................................................... 73
7.3
Data Parity Error Reporting Summary ................................................................ 74
7.4
System Error (SERR#) Reporting ....................................................................... 78
8.0
Exclusive Access ............................................................................................................. 81
8.1
Concurrent Locks ................................................................................................ 81
8.2
Acquiring Exclusive Access Across the 21150 ................................................... 81
8.3
Ending Exclusive Access .................................................................................... 82
9.0
PCI Bus Arbitration........................................................................................................... 85
9.1
Primary PCI Bus Arbitration ................................................................................ 85
9.2
Secondary PCI Bus Arbitration ........................................................................... 85
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter............................. 85
9.2.2
Secondary Bus Arbitration Using an External Arbiter............................. 87
iv
Preliminary
Datasheet