21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 46/164:

Read Prefetch Address Boundaries

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21150
4.6.3

Read Prefetch Address Boundaries

The 21150 imposes internal read address boundaries on read prefetching. When a read transaction
reaches one of these aligned address boundaries, the 21150 stops prefetching data, unless the target
signals a target disconnect before the read prefetch boundary is reached. When the 21150 finishes
transferring this read data to the initiator, it returns a target disconnect with the last data transfer,
unless the initiator completes the transaction before all prefetched read data is delivered. Any
leftover prefetched data is discarded.
Prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4KB address
boundary, or until the initiator deasserts FRAME#.
during read operations.
Table 19
shows the read prefetch address boundaries for read transactions during non-flow-through
mode.
Table 19. Read Prefetch Address Boundaries
Type of Transaction
Configuration read
I/O read
Memory read
Memory read
Memory read
Memory read line
Memory read line
Memory read multiple
Memory read multiple
4.6.4
Delayed Read Requests
The 21150 treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
placed in the read data queue directed toward the initiator bus interface and is transferred to the
initiator when the initiator repeats the read transaction.
When the 21150 accepts a delayed read request, it first samples the read address, read bus
command, and address parity. When IRDY# is asserted, the 21150 then samples the byte enable
bits for the first data phase. This information is entered into the delayed transaction queue. The
21150 terminates the transaction by signaling a target retry to the initiator. Upon reception of the
target retry, the initiator is required to continue to repeat the same read transaction until at least one
data transfer is completed, or until a target response other than a target retry (target abort, or master
abort) is received.
38
Section 4.6.6
Address Space
Cache Line Size
Nonprefetchable
Prefetchable
CLS
1, 2, 4, 8
Prefetchable
CLS = 1, 2, 4, 8
CLS
1, 2, 4, 8
CLS = 1, 2, 4, 8
CLS
1, 2, 4, 8
CLS = 1, 2, 4, 8
describes flow-through mode
Prefetch Aligned
Address Boundary
1 Dword (no prefetch)
1 Dword (no prefetch)
1 Dword (no prefetch)
16-Dword aligned
address boundary
Cache line address
boundary
16-Dword aligned
address boundary
Cache line boundary
Queue full
Second cache line
boundary
Preliminary
Datasheet