21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 49/164:

Prefetchable Delayed Read Transaction

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Figure 10. Prefetchable Delayed Read Transaction
CY0
Cycle
CY1
< 15ns >
p_clk
p_ad
Addr
p_cbe_l
6
p_frame_l
p_irdy_l
p_devsel_l
p_trdy_l
p_stop_l
s_clk
s_ad
s_cbe_l
s_frame_l
s_irdy_l
s_devsel_l
s_trdy_l
s_stop_l
When the master repeats the transaction and starts transferring prefetchable read data from 21150
data buffers while the read transaction on the target bus is still in progress and before a read
boundary is reached on the target bus, the read transaction starts operating in flow-through mode.
Because data is flowing through the data buffers from the target to the initiator, long read bursts can
then be sustained. In this case, the read transaction is allowed to continue until the initiator
terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer
fills, whichever comes first. When the buffer empties, the 21150 reflects the stalled condition to the
initiator by deasserting TRDY# until more read data is available; otherwise, the 21150 does not
insert any target wait states. When the initiator terminates the transaction, the deassertion of
FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data is discarded.
Figure 11
shows a flow-through prefetchable read transaction.
Preliminary
Datasheet
CY2
CY4
CY6
CY8
CY10
CY3
CY5
CY7
CY9
CY11
Addr
Addr
Byte Enables
6
Byte Enables
6
Addr
Data
Data
Data
Data
Data
6
0
CY12
CY14
CY16
CY18
CY20
CY13
CY15
CY17
CY19
CY21
Data
Data
Data
Data
Data
Data
Data
Data
Byte Enables
Data
Data
Data
73%
LJ-04847.AI4
21150
41