21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 50/164:

Flow-Through Prefetchable Read Transaction

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21150
Figure 11. Flow-Through Prefetchable Read Transaction
CY0
Cycle
CY1
<15ns>
p_clk
p_ad
Addr
p_cbe_l
6
p_frame_l
p_irdy_l
p_devsel_l
p_trdy_l
p_stop_l
s_clk
s_ad
s_cbe_l
s_frame_l
s_irdy_l
s_devsel_l
s_trdy_l
s_stop_l
The 21150 implements a discard timer that starts counting when the delayed read completion is at
the head of the delayed transaction queue, and the read data is at the head of the read data queue.
The initial value of this timer can be set to one of two values, selectable through both the primary
and secondary master timeout value bits in the bridge control register. If the initiator does not
repeat the read transaction before the discard timer expires, the 21150 discards the read transaction
and the read data from its queues. The 21150 also conditionally asserts p_serr_l (see
The 21150 has the capability to post multiple delayed read requests, up to a maximum of three in
each direction. If an initiator starts a read transaction that matches the address and read command
of a read transaction that is already queued, the current read command is not posted as it is already
contained in the delayed transaction queue.
See
Section 6.0
for a discussion of how delayed read transactions are ordered when crossing the
21150.
4.7
Configuration Transactions
Configuration transactions are used to initialize a PCI system. Every PCI device has a
configuration space that is accessed by configuration commands. All 21150 registers are accessible
in configuration space only.
42
CY2
CY4
CY6
CY8
CY10
CY3
CY5
CY7
CY9
Addr
Byte Enables
6
Addr
Data
Data
Data
Data
6
CY12
CY14
CY16
CY18
CY11
CY13
CY15
CY17
CY19
Data
Data
Data
Data
Byte Enables
Data
Data
Data
Data
Data
Data
0
78%
LJ-04848.AI4
Section
Preliminary
Datasheet
7.4).