21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

CaseQFP  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Page 54/164:

Special Cycles

Download datasheet (812Kb)Embed
PrevNext
21150
The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus
number register and the upper limit (inclusive) in the subordinate bus number register.
The bus command is a configuration read or write transaction.
The 21150 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream
to support upstream special cycle generation. A Type 1 configuration command is forwarded
upstream when the following conditions are met:
The low 2 address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the secondary
bus number register and the upper limit (inclusive) in the subordinate bus number register.
The device number in address bits AD<15:11> is equal to 11111b.
The function number in address bits AD<10:8> is equal to 111b.
The bus command is a configuration write transaction.
The 21150 forwards Type 1 to Type 1 configuration write transactions as delayed transactions.
Type 1 to Type 1 configuration write transactions are limited to a single data transfer.
4.7.4

Special Cycles

The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical
PCI systems. Special cycle transactions are ignored by a PCI-to-PCI bridge acting as a target and
are not forwarded across the bridge. Special cycle transactions can be generated from Type 1
configuration write transactions in either the upstream or the downstream direction.
The 21150 initiates a special cycle on the target bus when a Type 1 configuration write transaction
is detected on the initiating bus and the following conditions are met during the address phase:
The low 2 address bits on AD<1:0> are equal to 01b.
The device number in address bits AD<15:11> is equal to 11111b.
The function number in address bits AD<10:8> is equal to 111b.
The register number in address bits AD<7:2> is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in configuration
space for downstream forwarding or equal to the value in the primary bus number register in
configuration space for upstream forwarding.
The bus command on C/BE# is a configuration write command.
When the 21150 initiates the transaction on the target interface, the bus command is changed from
configuration write to special cycle. The address and data are forwarded unchanged. Devices that
use special cycles ignore the address and decode only the bus command. The data phase contains
the special cycle message. The transaction is forwarded as a delayed transaction, but in this case
the target response is not forwarded back (because special cycles result in a master abort). Once the
transaction is completed on the target bus, through detection of the master abort condition, the
21150 responds with TRDY# to the next attempt of the configuration transaction from the initiator.
If more than one data transfer is requested, the 21150 responds with a target disconnect operation
during the first data phase.
46
Preliminary
Datasheet