21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Figure 13. Delayed Write Transaction Terminated with Master Abort
CY0
Cycle
CY1
< 15ns >
p_clk
p_ad
Addr
p_cbe_l
p_frame_l
p_irdy_l
p_devsel_l
p_trdy_l
p_stop_l
s_clk
s_ad
s_cbe_l
s_frame_l
s_irdy_l
s_devsel_l
s_trdy_l
s_stop_l
When a master abort is received in response to a posted write transaction, the 21150 discards the
posted write data and makes no more attempts to deliver the data. The 21150 sets the received
master abort bit in the status register when the master abort is received on the primary bus, or it sets
the received master abort bit in the secondary status register when the master abort is received on
the secondary interface.
When a master abort is detected in response to a posted write transaction, and the master abort
mode bit is set, the 21150 also asserts p_serr_l if enabled by the SERR# enable bit in the command
register and if not disabled by the device-specific p_serr_l disable bit for master abort during
posted write transactions (that is, master abort mode = 1; SERR# enable bit = 1; and p_serr_l
disable bit for master aborts = 0.)
Note: When the 21150 performs a Type 1 to special cycle translation, a master abort is the expected
termination for the special cycle on the target bus. In this case, the master abort received bit is not
set, and the Type 1 configuration transaction is disconnected after the first data phase.
Preliminary
Datasheet
CY2
CY4
CY6
CY8
CY3
CY5
CY7
Data
Addr
Data
3
Byte Enables
3
Byte Enables
Addr
Data
3
Byte Enables
21150
CY10
CY12
CY14
CY16
CY9
CY11
CY13
CY15
Addr
Data
3
Byte Enables
91%
LJ-04849.AI4
49