21150-AB Intel Corporation, 21150-AB Datasheet - Page 57

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
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Preliminary
Figure 13. Delayed Write Transaction Terminated with Master Abort
Note: When the 21150 performs a Type 1 to special cycle translation, a master abort is the expected
Datasheet
When a master abort is received in response to a posted write transaction, the 21150 discards the
posted write data and makes no more attempts to deliver the data. The 21150 sets the received
master abort bit in the status register when the master abort is received on the primary bus, or it sets
the received master abort bit in the secondary status register when the master abort is received on
the secondary interface.
When a master abort is detected in response to a posted write transaction, and the master abort
mode bit is set, the 21150 also asserts p_serr_l if enabled by the SERR# enable bit in the command
register and if not disabled by the device-specific p_serr_l disable bit for master abort during
posted write transactions (that is, master abort mode = 1; SERR# enable bit = 1; and p_serr_l
disable bit for master aborts = 0.)
termination for the special cycle on the target bus. In this case, the master abort received bit is not
set, and the Type 1 configuration transaction is disconnected after the first data phase.
p_devsel_l
s_devsel_l
p_frame_l
s_frame_l
p_stop_l
s_stop_l
p_trdy_l
p_irdy_l
s_trdy_l
s_irdy_l
p_cbe_l
s_cbe_l
Cycle
p_clk
s_clk
p_ad
s_ad
< 15ns >
CY0
CY1
Addr
3
CY2
Byte Enables
Data
CY3
CY4
Addr
3
CY5
CY6
Addr
3
Byte Enables
CY7
Data
Byte Enables
Data
CY8
CY9
CY10
Addr
3
CY11
Byte Enables
Data
CY12
CY13
CY14
91%
CY15
LJ-04849.AI4
CY16
21150
49

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