21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Page 58/164:

Normal termination (upon deassertion of FRAME )

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21150
4.8.3
Target Termination Received by the 21150
When the 21150 initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types of termination:
Normal termination (upon deassertion of FRAME#)
Target retry
Target disconnect
Target abort
The 21150 handles these terminations in different ways, depending on the type of transaction being
performed.
4.8.3.1
Delayed Write Target Termination Response
When the 21150 initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator.
target termination that occurs during a delayed write transaction.
Table 21. 21150 Response to Delayed Write Target Termination
Normal
Target retry
Target disconnect
Target abort
The 21150 repeats a delayed write transaction until one of the following conditions is met:
The 21150 completes at least one data transfer.
The 21150 receives a master abort.
The 21150 receives a target abort.
The 21150 makes 2
After the 21150 makes 2
21150 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the
implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event
disable register. The 21150 stops initiating transactions in response to that delayed write
transaction. The delayed write request is discarded. Upon a subsequent write transaction attempt by
the initiator, the 21150 returns a target abort. See
conditions.
50
Table 21
shows the 21150 response to each type of
Target Termination
Return disconnect to initiator with first data transfer
only if multiple data phases requested.
Return target retry to initiator. Continue write attempts
to target.
Return disconnect to initiator with first data transfer
only if multiple data phases requested.
Return target abort to initiator.
Set received target abort bit in target interface status
register.
Set signaled target abort bit in initiator interface status
register.
24
write attempts resulting in a response of target retry.
24
attempts of the same delayed write transaction on the target bus, the
Section 7.4
21150 Response
for a description of system error
Preliminary
Datasheet