21150-AB Address Decoding - Intel Corporation

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
5.0

Address Decoding

The 21150 uses three address ranges that control I/O and memory transaction forwarding. These
address ranges are defined by base and limit address registers in the 21150 configuration space.
This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
5.1
Address Ranges
The 21150 uses the following address ranges that determine which I/O and memory transactions
are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to
the primary bus:
One 32-bit I/O address range
One 32-bit memory-mapped I/O (nonprefetchable memory)
One 64-bit prefetchable memory address range
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to
the secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the
secondary PCI bus to the primary PCI bus.
The 21150 uses a flat address space; that is, it does not perform any address translations. The
address space has no “gaps”—addresses that are not marked for downstream forwarding are
always forwarded upstream.
5.2
I/O Address Decoding
The 21150 uses the following mechanisms that are defined in the 21150 configuration space to
specify the I/O address space for downstream and upstream forwarding:
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
This section provides information on the I/O address registers and ISA
information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in 21150 configuration space. If the I/O enable bit is not set, all I/O transactions
initiated on the primary bus are ignored. To enable upstream forwarding of I/O transactions, the
master enable bit must be set in the command register. If the master enable bit is not set, the 21150
ignores all I/O and memory transactions initiated on the secondary bus. Setting the master enable
bit also allows upstream forwarding of memory transactions.
Preliminary
Datasheet
21150
mode.Section 5.4
provides
55

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