21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 73/164:

Transaction Ordering

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6.0

Transaction Ordering

To maintain data coherency and consistency, the 21150 complies with the ordering rules set forth in
the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge.
This chapter describes the ordering rules that control transaction forwarding across the 21150. For
a more detailed discussion of transaction ordering, see Appendix E of the PCI Local Bus
Specification, Revision 2.1.
6.1
Transactions Governed by Ordering Rules
Ordering relationships are established for the following classes of transactions crossing the 21150:
Posted write transactions, comprised of memory write and memory write and invalidate
transactions
Posted write transactions complete at the source before they complete at the destination; that
is, data is written into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write
transactions
Delayed write requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue. A delayed write transaction must complete on the target bus before
it completes on the initiator bus.
Delayed write completion transactions, also comprised of I/O write and configuration write
transactions
Delayed write completion transactions have been completed on the target bus, and the target
response is queued in the 21150 buffers. A delayed write completion transaction proceeds in
the direction opposite that of the original delayed write request; that is, a delayed write
completion transaction proceeds from the target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and configuration
read transactions
Delayed read requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, and
configuration read transactions
Delayed read completion transactions have been completed on the target bus, and the read data
has been queued in the 21150 read data buffers. A delayed read completion transaction
proceeds in the direction opposite that of the original delayed read request; that is, a delayed
read completion transaction proceeds from the target bus to the initiator bus.
The 21150 does not combine or merge write transactions:
The 21150 does not combine separate write transactions into a single write transaction—this
optimization is best implemented in the originating master.
The 21150 does not merge bytes on separate masked write transactions to the same Dword
address—this optimization is also best implemented in the originating master.
The 21150 does not collapse sequential write transactions to the same address into asingle
write transaction—the PCI Local Bus Specification does not permit this combining of
transactions.
Preliminary
Datasheet
21150
65