21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Table 24. Summary of Transaction Ordering (Sheet 2 of 2)
Pass
Posted Write
Delayed write
No
request
Delayed read
No
completion
Delayed write
Yes
completion
The following ordering rules describe the transaction relationships. Each ordering rule is followed
by an explanation, and the ordering rules are referred to by number in
rules apply to posted write transactions, delayed write and read requests, and delayed write and
read completion transactions crossing the 21150 in the same direction. Note that delayed
completion transactions cross the 21150 in the direction opposite that of the corresponding delayed
requests.
1. Posted write transactions must complete on the target bus in the order in which they were
received on the initiator bus.
The subsequent posted write transaction can be setting a flag that covers the data in the first
posted write transaction; if the second transaction were to complete before the first transaction,
a device checking the flag could subsequently consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted write
transaction must push the posted write data ahead of it. The posted write transaction must
complete on the target bus before the delayed read request can be attempted on the target bus.
The read transaction can be to the same location as the write data, so if the read transaction
were to pass the write transaction, it would return stale data.
3. A delayed read completion must “pull” ahead of previously queued posted write data traveling
in the same direction. In this case, the read data is traveling in the same direction as the write
data, and the initiator of the read transaction is on the same side of the 21150 as the target of
the write transaction. The posted write transaction must complete to the target before the read
data is returned to the initiator.
The read transaction can be to a status register of the initiator of the posted write data and
therefore should not complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data.
As in the case of posted memory write transactions, the delayed write transaction can be
setting a flag that covers the data in the posted write transaction; if the delayed write request
were to complete before the earlier posted write transaction, a device checking the flag could
subsequently consume stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write requests
and completions.
Otherwise, deadlocks may occur when bridges that support delayed transactions are used in
the same system with bridges that do not support delayed transactions. A fairness algorithm is
used to arbitrate between the posted write queue and the delayed transaction queue.
Preliminary
Datasheet
Delayed Read
Delayed Write
Request
Request
4
No
No
3
Yes
Yes
Yes
Yes
21150
Delayed Read
Delayed Write
Completion
Completion
Yes
Yes
No
No
No
No
Table
24. These ordering
67