21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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21150
Table 28
shows setting the data parity detected bit in the secondary status register, corresponding to
the secondary interface. This bit is set under the following conditions:
The 21150 must be a master on the secondary bus.
The parity error response bit in the bridge control register, corresponding
to the secondary interface, must be set.
The s_perr_l signal is detected asserted or a parity error is detected on the secondary bus.
Table 28. Setting the Secondary Interface Data Parity Detected Bit
Secondary
Data Parity
Detected Bit
0
Read
1
Read
0
Read
0
Read
0
Posted write
1
Posted write
0
Posted write
0
Posted write
0
Delayed write
1
Delayed write
0
Delayed write
0
Delayed write
1.
x = don’t care
Table 29
shows assertion of p_perr_l. This signal is set under the following conditions:
The 21150 is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity error response bit in the command register, corresponding to the primary interface,
must be set.
The 21150 detects a data parity error on the primary bus or detects s_perr_l asserted during the
completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 29. Assertion of p_perr_l (Sheet 1 of 2)
p_perr_l
1 (deasserted)
Read
1
Read
0 (asserted)
Read
1
Read
0
Posted write
1
Posted write
76
Transaction Type
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Transaction Type
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Primary/Secondary
Bus Where Error
Parity Error
Was Detected
Response Bits
1
Primary
x/x
Secondary
x/1
Primary
x/x
Secondary
x/x
Primary
x/x
Secondary
x/1
Primary
x/x
Secondary
x/x
Primary
x/x
Secondary
x/1
Primary
x/x
Secondary
x/x
Primary/Secondary
Bus Where Error
Parity Error
Was Detected
Response Bits
1
Primary
x/x
Secondary
x/x
Primary
1/x
Secondary
x/x
Primary
1/x
Secondary
x/1
Preliminary
Datasheet