21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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Page 86/164:

System Error (SERR ) Reporting

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21150
The parity error response bit on the command register and the parity error response bit on the
bridge control register must both be set.
The SERR# enable bit must be set in the command register.
Table 31. Assertion of p_serr_l for Data Parity Errors
p_serr_l
1 (deasserted)
Read
1
Read
1
Read
1
Read
1
Posted write
2
0
Posted write
3
0
Posted write
1
Posted write
1
Delayed write
1
Delayed write
1
Delayed write
1
Delayed write
1.
x = don’t care
2.
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
7.4
System Error (SERR#) Reporting
The 21150 uses the p_serr_l signal to report conditionally a number of system error conditions in
addition to the special case parity error conditions described in
Whenever the assertion of p_serr_l is discussed in this document, it is assumed that the following
conditions apply:
For the 21150 to assert p_serr_l for any reason, the SERR# enable bit must be set in the
command register.
Whenever the 21150 asserts p_serr_l, the 21150 must also set the signaled system error bit in
the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, the 21150 asserts p_serr_l
when it detects the secondary SERR# input, s_serr_l, asserted and the SERR# forward enable bit is
set in the bridge control register. In addition, the 21150 also sets the received system error bit in the
secondary status register.
The 21150 also conditionally asserts p_serr_l for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
78
Transaction Type
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
24
attempts to deliver (2
Primary/Secondary
Bus Where Error
Parity Error
Was Detected
Response Bits
1
Primary
x/x
Secondary
x/x
Primary
x/x
Secondary
x/x
Primary
x/x
Secondary
1/1
Primary
1/1
Secondary
x/x
Primary
x/x
Secondary
x/x
Primary
x/x
Secondary
x/x
Section
7.2.3.
24
target retries received)
Preliminary
Datasheet